Parameterized modules with parameter keyword in Verilog - Step-by-Step Execution

Concept Flow - Parameterized modules with parameter keyword

Define module with parameter

↓

Parameter gets default value

↓

Instantiate module

↓

Override parameter if needed

↓

Module uses parameter in code

↓

Simulation or synthesis uses parameterized value

This flow shows how a Verilog module is defined with a parameter, instantiated with or without overriding it, and how the parameter controls module behavior.

Execution Sample

Verilog

module adder #(parameter WIDTH = 4) (
  input wire [WIDTH-1:0] a, b,
  output wire [WIDTH-1:0] sum
);
  assign sum = a + b;
endmodule

Defines a parameterized adder module where WIDTH controls the bit-width of inputs and output.

Execution Table

Step	Action	Parameter WIDTH	Input a	Input b	Sum Calculation	Output sum
1	Module defined with default WIDTH=4	4	-	-	-	-
2	Instantiate adder with default WIDTH	4	4'b0011 (3)	4'b0101 (5)	3 + 5 = 8	4'b1000 (8)
3	Instantiate adder with WIDTH=8 override	8	8'b00000011 (3)	8'b00000101 (5)	3 + 5 = 8	8'b00001000 (8)
4	Simulation ends	-	-	-	-	-

💡 Simulation ends after showing outputs for default and overridden parameter instances.

Variable Tracker

Variable	Start	After Step 2	After Step 3	Final
WIDTH	4 (default)	4	8 (overridden)	8
a	-	4'b0011	8'b00000011	8'b00000011
b	-	4'b0101	8'b00000101	8'b00000101
sum	-	4'b1000	8'b00001000	8'b00001000

Key Moments - 3 Insights

Why does the sum output width change when WIDTH is overridden?

Because the parameter WIDTH controls the bit-width of inputs and output. When WIDTH is overridden to 8, inputs and output become 8 bits wide, as shown in execution_table rows 2 and 3.

What happens if we don't override the parameter WIDTH during instantiation?

The module uses the default WIDTH value defined in the module (4 in this case), as shown in execution_table row 2.

Can parameters be used inside the module code?

Yes, parameters like WIDTH are used inside the module to define sizes and behavior, for example in input/output widths and calculations, as seen in the sum calculation column.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3, what is the value of WIDTH?

A 0

B 4

C 8

D Undefined

💡 Hint

Check the 'Parameter WIDTH' column at Step 3 in the execution_table.

At which step does the module use the default parameter value?

A Step 2

B Step 1

C Step 3

D Step 4

💡 Hint

Look at the 'Parameter WIDTH' column and see where WIDTH is 4 without override.

If we change WIDTH to 6 during instantiation, what will happen to the output sum width?

A It stays 4 bits

B It becomes 6 bits

C It becomes 8 bits

D It becomes 1 bit

💡 Hint

Refer to variable_tracker for WIDTH changes and how it affects sum width.

Concept Snapshot

module name #(parameter PARAM_NAME = default_value) (ports);
  // Use PARAM_NAME inside module
endmodule

- Parameters set default values
- Override parameters during instantiation
- Controls module behavior and sizes
- Helps create reusable modules

Full Transcript

This visual execution shows how Verilog modules use the parameter keyword to create flexible designs. The module 'adder' is defined with a parameter WIDTH defaulting to 4. When instantiated without override, WIDTH remains 4, so inputs and outputs are 4 bits wide. When instantiated with WIDTH=8, inputs and outputs become 8 bits wide. The execution table traces each step, showing parameter values, inputs, sum calculation, and outputs. The variable tracker shows how WIDTH and signals change. Key moments clarify common confusions about default vs overridden parameters and their use inside the module. The quiz tests understanding of parameter values at different steps and effects of changing WIDTH. This helps beginners see how parameters make modules reusable and adaptable.

Practice

1. What is the main purpose of using the parameter keyword in a Verilog module?

easy

A. To specify the clock frequency inside the module

B. To define constants that can be changed when the module is instantiated

C. To declare input and output ports of the module

D. To create variables that change during simulation

Solution

1. Step 1: Understand the role of parameter

   The parameter keyword defines constants inside a module that can be set when the module is created.

2. Step 2: Compare with other options

   Input/output ports are declared with input and output, not parameter. Clock frequency is not set by parameter alone. Variables that change during simulation are declared differently.

3. Final Answer:

   To define constants that can be changed when the module is instantiated -> Option B

4. Quick Check:

   Parameter = adjustable constant [OK]

Hint: Parameters are like adjustable settings for modules [OK]

Common Mistakes:

• Confusing parameters with input/output ports
• Thinking parameters change during simulation
• Assuming parameters set clock frequency directly

2. Which of the following is the correct syntax to declare a parameter named WIDTH with a default value of 8 inside a Verilog module?

easy

A. define WIDTH = 8;

B. param WIDTH = 8;

C. parameter WIDTH : 8;

D. parameter WIDTH = 8;

Solution

1. Step 1: Recall Verilog parameter syntax

   The correct way to declare a parameter is using the keyword parameter followed by the name, an equals sign, and the value, ending with a semicolon.

2. Step 2: Check each option

   parameter WIDTH = 8; matches the correct syntax. param WIDTH = 8; uses incorrect keyword param. parameter WIDTH : 8; uses colon instead of equals. define WIDTH = 8; uses define which is for macros, not parameters.

3. Final Answer:

   parameter WIDTH = 8; -> Option D

4. Quick Check:

   Parameter syntax = keyword + name + = + value [OK]

Hint: Remember: parameter name = value; [OK]

Common Mistakes:

• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='
• Confusing parameters with macros (#define)

3. Given the following module and instantiation, what is the width of the output out?

module my_module #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

my_module #(.WIDTH(6)) instance1 (.in(6'b101010), .out(out_signal));

medium

A. 4 bits

B. 8 bits

C. 6 bits

D. Default width 1 bit

Solution

1. Step 1: Identify parameter override in instantiation

   The module has a default parameter WIDTH=4, but the instantiation overrides it with WIDTH=6.

2. Step 2: Determine output width from parameter

   The output width is defined as [WIDTH-1:0], so with WIDTH=6, output is 6 bits wide.

3. Final Answer:

   6 bits -> Option C

4. Quick Check:

   Parameter override sets WIDTH=6 [OK]

Hint: Check parameter override in #(...) during instantiation [OK]

Common Mistakes:

• Ignoring parameter override and using default
• Assuming output width is always 1 bit
• Confusing input width with output width

4. Identify the error in the following Verilog code snippet:

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] sum);
  assign sum = a + b;
endmodule

adder #(WIDTH=16) my_adder (.a(a_signal), .b(b_signal), .sum(sum_signal));

medium

A. Parameter override syntax is incorrect in instantiation

B. Missing semicolon after module declaration

C. Input and output port widths are not declared properly

D. Addition operation is invalid for vectors

Solution

1. Step 1: Check parameter override syntax

   The correct syntax for parameter override uses dot notation with parentheses: #(.WIDTH(16)), not #(WIDTH=16).

2. Step 2: Verify other parts

   Semicolons and port widths are correct. Addition on vectors is valid in Verilog.

3. Final Answer:

   Parameter override syntax is incorrect in instantiation -> Option A

4. Quick Check:

   Use #(.PARAM(value)) for parameter override [OK]

Hint: Use #(.PARAM(value)) syntax for parameters [OK]

Common Mistakes:

• Using = instead of ( ) in parameter override
• Forgetting dot before parameter name
• Assuming addition on vectors is invalid

5. You want to create a parameterized Verilog module shift_reg that shifts input bits by a configurable amount SHIFT. Which of the following module declarations correctly uses the parameter keyword and allows setting SHIFT during instantiation?

hard

A. module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

B. module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

C. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

D. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

Solution

1. Step 1: Check parameter declaration syntax

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule correctly declares parameter SHIFT = 2 inside #(...) after module name, which is the standard syntax.

2. Step 2: Validate other options

   module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule incorrectly places parameter inside port list. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses invalid keyword param. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses colon instead of equals.

3. Final Answer:

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule -> Option A

4. Quick Check:

   Parameter with default value inside #(parameter ...) [OK]

Hint: Declare parameters inside #(parameter NAME = value) [OK]

Common Mistakes:

• Placing parameter inside port list
• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='