Parameterized modules with parameter keyword in Verilog - Mini Project: Build & Apply

Parameterized modules with parameter keyword in Verilog

📖 Scenario: You are designing a simple digital circuit that can add two numbers. You want to make the bit-width of the numbers flexible so the same design can be used for different sizes.

🎯 Goal: Build a Verilog module called Adder that uses the parameter keyword to set the bit-width of the inputs and output. Then create a testbench to check the output for a specific bit-width.

📋 What You'll Learn

Create a parameterized module Adder with a parameter WIDTH defaulting to 8

Use the parameter WIDTH to define the input and output bit-widths

Create a testbench module TestAdder that instantiates Adder with WIDTH=4

Assign example values to inputs and display the output

💡 Why This Matters

🌍 Real World

Parameterized modules let hardware designers reuse code for different data sizes without rewriting logic. This saves time and reduces errors.

💼 Career

Understanding parameterized modules is essential for FPGA and ASIC design jobs where flexible, reusable hardware components are needed.

1

Create the parameterized Adder module

Write a Verilog module named Adder with a parameter WIDTH set to 8. Declare inputs a and b and output sum all with bit-width WIDTH.

Verilog

module Adder #(parameter WIDTH = 8) (
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] b,
    output [WIDTH-1:0] sum
);

// Your code here

endmodule

Hint

Use parameter WIDTH = 8 after the module name and use [WIDTH-1:0] for input and output widths.

2

Add the sum logic using the parameter

Inside the Adder module, assign sum to be the addition of a and b using the parameter WIDTH.

Verilog

module Adder #(parameter WIDTH = 8) (
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] b,
    output [WIDTH-1:0] sum
);

assign sum = a + b;  // Your code here

endmodule

Hint

Use an assign statement to add a and b and assign to sum.

3

Create a testbench module to test Adder with WIDTH=4

Write a testbench module named TestAdder. Instantiate Adder with parameter WIDTH=4. Declare reg [3:0] a and b, and wire [3:0] sum. Assign a = 4'b0011 and b = 4'b0101.

Verilog

module Adder #(parameter WIDTH = 8) (
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] b,
    output [WIDTH-1:0] sum
);

assign sum = a + b;

endmodule

module TestAdder();
    reg [3:0] a;
    reg [3:0] b;
    wire [3:0] sum;

    Adder #(4) uut (.a(a), .b(b), .sum(sum));

    initial begin
        a = 4'b0011;
        b = 4'b0101;
        // Your code here
    end
endmodule

Hint

Use reg for inputs and wire for output. Instantiate Adder with #(4) to set WIDTH=4.

4

Display the sum output in the testbench

In the initial block of TestAdder, add a $display statement to print the values of a, b, and sum in binary format.

Verilog

module Adder #(parameter WIDTH = 8) (
    input [WIDTH-1:0] a,
    input [WIDTH-1:0] b,
    output [WIDTH-1:0] sum
);

assign sum = a + b;

endmodule

module TestAdder();
    reg [3:0] a;
    reg [3:0] b;
    wire [3:0] sum;

    Adder #(4) uut (.a(a), .b(b), .sum(sum));

    initial begin
        a = 4'b0011;
        b = 4'b0101;
        $display("a = %b, b = %b, sum = %b", a, b, sum);  // Your code here
    end
endmodule

Hint

Use $display("a = %b, b = %b, sum = %b", a, b, sum); to print binary values.

Practice

1. What is the main purpose of using the parameter keyword in a Verilog module?

easy

A. To specify the clock frequency inside the module

B. To define constants that can be changed when the module is instantiated

C. To declare input and output ports of the module

D. To create variables that change during simulation

Solution

1. Step 1: Understand the role of parameter

   The parameter keyword defines constants inside a module that can be set when the module is created.

2. Step 2: Compare with other options

   Input/output ports are declared with input and output, not parameter. Clock frequency is not set by parameter alone. Variables that change during simulation are declared differently.

3. Final Answer:

   To define constants that can be changed when the module is instantiated -> Option B

4. Quick Check:

   Parameter = adjustable constant [OK]

Hint: Parameters are like adjustable settings for modules [OK]

Common Mistakes:

• Confusing parameters with input/output ports
• Thinking parameters change during simulation
• Assuming parameters set clock frequency directly

2. Which of the following is the correct syntax to declare a parameter named WIDTH with a default value of 8 inside a Verilog module?

easy

A. define WIDTH = 8;

B. param WIDTH = 8;

C. parameter WIDTH : 8;

D. parameter WIDTH = 8;

Solution

1. Step 1: Recall Verilog parameter syntax

   The correct way to declare a parameter is using the keyword parameter followed by the name, an equals sign, and the value, ending with a semicolon.

2. Step 2: Check each option

   parameter WIDTH = 8; matches the correct syntax. param WIDTH = 8; uses incorrect keyword param. parameter WIDTH : 8; uses colon instead of equals. define WIDTH = 8; uses define which is for macros, not parameters.

3. Final Answer:

   parameter WIDTH = 8; -> Option D

4. Quick Check:

   Parameter syntax = keyword + name + = + value [OK]

Hint: Remember: parameter name = value; [OK]

Common Mistakes:

• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='
• Confusing parameters with macros (#define)

3. Given the following module and instantiation, what is the width of the output out?

module my_module #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

my_module #(.WIDTH(6)) instance1 (.in(6'b101010), .out(out_signal));

medium

A. 4 bits

B. 8 bits

C. 6 bits

D. Default width 1 bit

Solution

1. Step 1: Identify parameter override in instantiation

   The module has a default parameter WIDTH=4, but the instantiation overrides it with WIDTH=6.

2. Step 2: Determine output width from parameter

   The output width is defined as [WIDTH-1:0], so with WIDTH=6, output is 6 bits wide.

3. Final Answer:

   6 bits -> Option C

4. Quick Check:

   Parameter override sets WIDTH=6 [OK]

Hint: Check parameter override in #(...) during instantiation [OK]

Common Mistakes:

• Ignoring parameter override and using default
• Assuming output width is always 1 bit
• Confusing input width with output width

4. Identify the error in the following Verilog code snippet:

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] sum);
  assign sum = a + b;
endmodule

adder #(WIDTH=16) my_adder (.a(a_signal), .b(b_signal), .sum(sum_signal));

medium

A. Parameter override syntax is incorrect in instantiation

B. Missing semicolon after module declaration

C. Input and output port widths are not declared properly

D. Addition operation is invalid for vectors

Solution

1. Step 1: Check parameter override syntax

   The correct syntax for parameter override uses dot notation with parentheses: #(.WIDTH(16)), not #(WIDTH=16).

2. Step 2: Verify other parts

   Semicolons and port widths are correct. Addition on vectors is valid in Verilog.

3. Final Answer:

   Parameter override syntax is incorrect in instantiation -> Option A

4. Quick Check:

   Use #(.PARAM(value)) for parameter override [OK]

Hint: Use #(.PARAM(value)) syntax for parameters [OK]

Common Mistakes:

• Using = instead of ( ) in parameter override
• Forgetting dot before parameter name
• Assuming addition on vectors is invalid

5. You want to create a parameterized Verilog module shift_reg that shifts input bits by a configurable amount SHIFT. Which of the following module declarations correctly uses the parameter keyword and allows setting SHIFT during instantiation?

hard

A. module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

B. module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

C. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

D. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

Solution

1. Step 1: Check parameter declaration syntax

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule correctly declares parameter SHIFT = 2 inside #(...) after module name, which is the standard syntax.

2. Step 2: Validate other options

   module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule incorrectly places parameter inside port list. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses invalid keyword param. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses colon instead of equals.

3. Final Answer:

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule -> Option A

4. Quick Check:

   Parameter with default value inside #(parameter ...) [OK]

Hint: Declare parameters inside #(parameter NAME = value) [OK]

Common Mistakes:

• Placing parameter inside port list
• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='