Parameterized modules with parameter keyword in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a parameter named WIDTH with a default value of 8.

Verilog

module my_module #(parameter [1] = 8) (); endmodule

Drag options to blanks, or click blank then click option'

ADEPTH

BSIZE

CLENGTH

DWIDTH

Attempts:

3 left

💡 Hint

Common Mistakes

Using a different parameter name than WIDTH.

The parameter name is WIDTH as specified in the module.

2fill in blank

medium

Complete the code to instantiate my_module with WIDTH set to 16.

Verilog

my_module #(.WIDTH([1])) instance_name ();

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A16

B8

C32

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Using the default value 8 instead of 16.

To override the parameter WIDTH to 16, use .WIDTH(16) in the instantiation.

3fill in blank

hard

Fix the error in the parameter declaration by completing the code.

Verilog

module my_module #(parameter [1] 8) (); endmodule

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AWIDTH :

BWIDTH =

CWIDTH ==

DWIDTH :=

Attempts:

3 left

💡 Hint

Common Mistakes

Using ':=' or '==' instead of '='.

The correct syntax for parameter assignment is parameter NAME = value.

4fill in blank

hard

Fill both blanks to declare two parameters WIDTH and DEPTH with default values 8 and 4.

Verilog

module my_module #(parameter [1] = 8, parameter [2] = 4) (); endmodule

Drag options to blanks, or click blank then click option'

AWIDTH

BSIZE

CDEPTH

DLENGTH

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing parameter names or forgetting commas.

The parameters are named WIDTH and DEPTH with values 8 and 4 respectively.

5fill in blank

hard

Fill all three blanks to instantiate my_module with WIDTH=16, DEPTH=4, and SIZE=32 parameters.

Verilog

my_module #(.WIDTH([1]), .DEPTH([2]), .SIZE([3])) instance ();

Drag options to blanks, or click blank then click option'

A8

B16

C32

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up parameter values or names.

The parameters are set as WIDTH=16, DEPTH=4, and SIZE=32 in the instantiation.

Practice

1. What is the main purpose of using the parameter keyword in a Verilog module?

easy

A. To specify the clock frequency inside the module

B. To define constants that can be changed when the module is instantiated

C. To declare input and output ports of the module

D. To create variables that change during simulation

Solution

1. Step 1: Understand the role of parameter

   The parameter keyword defines constants inside a module that can be set when the module is created.

2. Step 2: Compare with other options

   Input/output ports are declared with input and output, not parameter. Clock frequency is not set by parameter alone. Variables that change during simulation are declared differently.

3. Final Answer:

   To define constants that can be changed when the module is instantiated -> Option B

4. Quick Check:

   Parameter = adjustable constant [OK]

Hint: Parameters are like adjustable settings for modules [OK]

Common Mistakes:

• Confusing parameters with input/output ports
• Thinking parameters change during simulation
• Assuming parameters set clock frequency directly

2. Which of the following is the correct syntax to declare a parameter named WIDTH with a default value of 8 inside a Verilog module?

easy

A. define WIDTH = 8;

B. param WIDTH = 8;

C. parameter WIDTH : 8;

D. parameter WIDTH = 8;

Solution

1. Step 1: Recall Verilog parameter syntax

   The correct way to declare a parameter is using the keyword parameter followed by the name, an equals sign, and the value, ending with a semicolon.

2. Step 2: Check each option

   parameter WIDTH = 8; matches the correct syntax. param WIDTH = 8; uses incorrect keyword param. parameter WIDTH : 8; uses colon instead of equals. define WIDTH = 8; uses define which is for macros, not parameters.

3. Final Answer:

   parameter WIDTH = 8; -> Option D

4. Quick Check:

   Parameter syntax = keyword + name + = + value [OK]

Hint: Remember: parameter name = value; [OK]

Common Mistakes:

• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='
• Confusing parameters with macros (#define)

3. Given the following module and instantiation, what is the width of the output out?

module my_module #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

my_module #(.WIDTH(6)) instance1 (.in(6'b101010), .out(out_signal));

medium

A. 4 bits

B. 8 bits

C. 6 bits

D. Default width 1 bit

Solution

1. Step 1: Identify parameter override in instantiation

   The module has a default parameter WIDTH=4, but the instantiation overrides it with WIDTH=6.

2. Step 2: Determine output width from parameter

   The output width is defined as [WIDTH-1:0], so with WIDTH=6, output is 6 bits wide.

3. Final Answer:

   6 bits -> Option C

4. Quick Check:

   Parameter override sets WIDTH=6 [OK]

Hint: Check parameter override in #(...) during instantiation [OK]

Common Mistakes:

• Ignoring parameter override and using default
• Assuming output width is always 1 bit
• Confusing input width with output width

4. Identify the error in the following Verilog code snippet:

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] sum);
  assign sum = a + b;
endmodule

adder #(WIDTH=16) my_adder (.a(a_signal), .b(b_signal), .sum(sum_signal));

medium

A. Parameter override syntax is incorrect in instantiation

B. Missing semicolon after module declaration

C. Input and output port widths are not declared properly

D. Addition operation is invalid for vectors

Solution

1. Step 1: Check parameter override syntax

   The correct syntax for parameter override uses dot notation with parentheses: #(.WIDTH(16)), not #(WIDTH=16).

2. Step 2: Verify other parts

   Semicolons and port widths are correct. Addition on vectors is valid in Verilog.

3. Final Answer:

   Parameter override syntax is incorrect in instantiation -> Option A

4. Quick Check:

   Use #(.PARAM(value)) for parameter override [OK]

Hint: Use #(.PARAM(value)) syntax for parameters [OK]

Common Mistakes:

• Using = instead of ( ) in parameter override
• Forgetting dot before parameter name
• Assuming addition on vectors is invalid

5. You want to create a parameterized Verilog module shift_reg that shifts input bits by a configurable amount SHIFT. Which of the following module declarations correctly uses the parameter keyword and allows setting SHIFT during instantiation?

hard

A. module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

B. module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

C. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

D. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

Solution

1. Step 1: Check parameter declaration syntax

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule correctly declares parameter SHIFT = 2 inside #(...) after module name, which is the standard syntax.

2. Step 2: Validate other options

   module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule incorrectly places parameter inside port list. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses invalid keyword param. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses colon instead of equals.

3. Final Answer:

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule -> Option A

4. Quick Check:

   Parameter with default value inside #(parameter ...) [OK]

Hint: Declare parameters inside #(parameter NAME = value) [OK]

Common Mistakes:

• Placing parameter inside port list
• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='