Parameterized modules with parameter keyword in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of parameterized module instantiation

What is the output of the following Verilog code when simulated?

Verilog

module adder #(parameter WIDTH = 4) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] sum);
  assign sum = a + b;
endmodule

module test;
  wire [7:0] result;
  reg [7:0] x = 8'd15, y = 8'd10;
  adder #(.WIDTH(8)) my_adder(.a(x), .b(y), .sum(result));
  initial begin
    #1 $display("Result = %d", result);
  end
endmodule

A Result = 0

B Result = 5

C Result = 25

D Simulation error due to width mismatch

💡 Hint

Check the parameter WIDTH and how it affects the input and output widths.

The parameter WIDTH is set to 8, so inputs and output are 8 bits wide. Adding 15 and 10 results in 25, which fits in 8 bits.

❓ Predict Output

intermediate

Effect of default parameter in module

What will be the output of this Verilog code snippet?

Verilog

module multiplier #(parameter FACTOR = 3) (input [3:0] in, output [7:0] out);
  assign out = in * FACTOR;
endmodule

module test;
  reg [3:0] val = 4'd4;
  wire [7:0] result;
  multiplier mul(.in(val), .out(result));
  initial begin
    #1 $display("Result = %d", result);
  end
endmodule

A Result = 0

B Result = 12

C Result = 16

D Result = 7

💡 Hint

Look at the default parameter FACTOR and the input value.

The default FACTOR is 3, input is 4, so output is 4 * 3 = 12.

🔧 Debug

advanced

Identify the error in parameterized module instantiation

What error will this Verilog code produce when compiled?

Verilog

module shift #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in << 1;
endmodule

module test;
  wire [3:0] result;
  reg [3:0] data = 4'b1010;
  shift #(.WIDTH(3)) sh(.in(data), .out(result));
endmodule

A Error: Output port width mismatch

B No error, simulation runs correctly

C Error: Missing semicolon in module definition

D Error: Width mismatch between input and parameter WIDTH

💡 Hint

Check the widths of input and output ports versus the parameter WIDTH.

The parameter WIDTH is set to 3, but input 'data' is 4 bits wide. This causes a width mismatch error during instantiation.

📝 Syntax

advanced

Correct syntax for parameter override in module instantiation

Which option shows the correct way to override a parameter WIDTH to 16 during module instantiation?

Verilog

module counter #(parameter WIDTH = 8) (input clk, output reg [WIDTH-1:0] count);
  always @(posedge clk) count <= count + 1;
endmodule

module test;
  wire [15:0] cnt;
  reg clk = 0;
  // Instantiate counter here
endmodule

A counter #(.WIDTH(16)) c(.clk(clk), .count(cnt));

B counter #(WIDTH=16) c(.clk(clk), .count(cnt));

C counter #(.WIDTH=16) c(.clk(clk), .count(cnt));

D counter #(.WIDTH(16)) c(clk, cnt);

💡 Hint

Remember the syntax for named parameter override uses .param_name(value).

The correct syntax uses #(.WIDTH(16)) with parentheses, not equal signs or missing parentheses.

🚀 Application

expert

Determine the number of bits in output for nested parameterized modules

Given the following Verilog code, what is the width of the output wire 'final_out'?

Verilog

module stage #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in + 1;
endmodule

module pipeline #(parameter STAGES = 3, WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  wire [WIDTH-1:0] stage_outs [0:STAGES];
  assign stage_outs[0] = in;
  genvar i;
  generate
    for (i = 0; i < STAGES; i = i + 1) begin : gen_stages
      stage #(.WIDTH(WIDTH)) s(.in(stage_outs[i]), .out(stage_outs[i+1]));
    end
  endgenerate
  assign out = stage_outs[STAGES];
endmodule

module test;
  wire [7:0] final_out;
  reg [7:0] input_val = 8'd10;
  pipeline #(.STAGES(5), .WIDTH(8)) p(.in(input_val), .out(final_out));
endmodule

A 8 bits

B 5 bits

C 20 bits

D 4 bits

💡 Hint

Check how the WIDTH parameter is passed through the nested modules.

The WIDTH parameter is set to 8 in the pipeline instantiation and passed to each stage. The output width remains 8 bits.

Practice

1. What is the main purpose of using the parameter keyword in a Verilog module?

easy

A. To specify the clock frequency inside the module

B. To define constants that can be changed when the module is instantiated

C. To declare input and output ports of the module

D. To create variables that change during simulation

Solution

1. Step 1: Understand the role of parameter

   The parameter keyword defines constants inside a module that can be set when the module is created.

2. Step 2: Compare with other options

   Input/output ports are declared with input and output, not parameter. Clock frequency is not set by parameter alone. Variables that change during simulation are declared differently.

3. Final Answer:

   To define constants that can be changed when the module is instantiated -> Option B

4. Quick Check:

   Parameter = adjustable constant [OK]

Hint: Parameters are like adjustable settings for modules [OK]

Common Mistakes:

• Confusing parameters with input/output ports
• Thinking parameters change during simulation
• Assuming parameters set clock frequency directly

2. Which of the following is the correct syntax to declare a parameter named WIDTH with a default value of 8 inside a Verilog module?

easy

A. define WIDTH = 8;

B. param WIDTH = 8;

C. parameter WIDTH : 8;

D. parameter WIDTH = 8;

Solution

1. Step 1: Recall Verilog parameter syntax

   The correct way to declare a parameter is using the keyword parameter followed by the name, an equals sign, and the value, ending with a semicolon.

2. Step 2: Check each option

   parameter WIDTH = 8; matches the correct syntax. param WIDTH = 8; uses incorrect keyword param. parameter WIDTH : 8; uses colon instead of equals. define WIDTH = 8; uses define which is for macros, not parameters.

3. Final Answer:

   parameter WIDTH = 8; -> Option D

4. Quick Check:

   Parameter syntax = keyword + name + = + value [OK]

Hint: Remember: parameter name = value; [OK]

Common Mistakes:

• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='
• Confusing parameters with macros (#define)

3. Given the following module and instantiation, what is the width of the output out?

module my_module #(parameter WIDTH = 4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  assign out = in;
endmodule

my_module #(.WIDTH(6)) instance1 (.in(6'b101010), .out(out_signal));

medium

A. 4 bits

B. 8 bits

C. 6 bits

D. Default width 1 bit

Solution

1. Step 1: Identify parameter override in instantiation

   The module has a default parameter WIDTH=4, but the instantiation overrides it with WIDTH=6.

2. Step 2: Determine output width from parameter

   The output width is defined as [WIDTH-1:0], so with WIDTH=6, output is 6 bits wide.

3. Final Answer:

   6 bits -> Option C

4. Quick Check:

   Parameter override sets WIDTH=6 [OK]

Hint: Check parameter override in #(...) during instantiation [OK]

Common Mistakes:

• Ignoring parameter override and using default
• Assuming output width is always 1 bit
• Confusing input width with output width

4. Identify the error in the following Verilog code snippet:

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-1:0] sum);
  assign sum = a + b;
endmodule

adder #(WIDTH=16) my_adder (.a(a_signal), .b(b_signal), .sum(sum_signal));

medium

A. Parameter override syntax is incorrect in instantiation

B. Missing semicolon after module declaration

C. Input and output port widths are not declared properly

D. Addition operation is invalid for vectors

Solution

1. Step 1: Check parameter override syntax

   The correct syntax for parameter override uses dot notation with parentheses: #(.WIDTH(16)), not #(WIDTH=16).

2. Step 2: Verify other parts

   Semicolons and port widths are correct. Addition on vectors is valid in Verilog.

3. Final Answer:

   Parameter override syntax is incorrect in instantiation -> Option A

4. Quick Check:

   Use #(.PARAM(value)) for parameter override [OK]

Hint: Use #(.PARAM(value)) syntax for parameters [OK]

Common Mistakes:

• Using = instead of ( ) in parameter override
• Forgetting dot before parameter name
• Assuming addition on vectors is invalid

5. You want to create a parameterized Verilog module shift_reg that shifts input bits by a configurable amount SHIFT. Which of the following module declarations correctly uses the parameter keyword and allows setting SHIFT during instantiation?

hard

A. module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

B. module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

C. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

D. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule

Solution

1. Step 1: Check parameter declaration syntax

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule correctly declares parameter SHIFT = 2 inside #(...) after module name, which is the standard syntax.

2. Step 2: Validate other options

   module shift_reg (parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule incorrectly places parameter inside port list. module shift_reg #(param SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses invalid keyword param. module shift_reg #(parameter SHIFT : 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule uses colon instead of equals.

3. Final Answer:

   module shift_reg #(parameter SHIFT = 2) (input [7:0] in, output [7:0] out); assign out = in << SHIFT; endmodule -> Option A

4. Quick Check:

   Parameter with default value inside #(parameter ...) [OK]

Hint: Declare parameters inside #(parameter NAME = value) [OK]

Common Mistakes:

• Placing parameter inside port list
• Using 'param' instead of 'parameter'
• Using colon ':' instead of equals '='