Module instantiation syntax in Verilog - Step-by-Step Execution

Concept Flow - Module instantiation syntax

Define module with ports

↓

Write module instantiation

↓

Connect ports by position or name

↓

Use instance in design

↓

Simulation or synthesis uses instance

This flow shows how a module is defined, then instantiated by connecting its ports, and finally used in a design.

Execution Sample

Verilog

module AND2(input A, input B, output Y);
  assign Y = A & B;
endmodule

module top();
  wire in1, in2, out;
  AND2 u1(.A(in1), .B(in2), .Y(out));
endmodule

This code defines a 2-input AND gate module and instantiates it by connecting signals by name.

Execution Table

Step	Action	Code Line	Result
1	Define module AND2 with ports A, B, Y	module AND2(input A, input B, output Y);	Module AND2 created
2	Assign output Y as A AND B	assign Y = A & B;	Logic defined inside AND2
3	End module definition	endmodule	Module AND2 definition complete
4	Instantiate AND2 as u1 with named port connections	AND2 u1(.A(in1), .B(in2), .Y(out));	Instance u1 created with ports connected
5	Simulation/synthesis uses instance u1	N/A	u1 behaves as AND gate with inputs in1, in2 and output out
6	End of instantiation example	N/A	Execution stops

💡 All steps completed, module instantiated and ready for use

Variable Tracker

Variable	Start	After Step 4	Final
Module AND2	Not defined	Defined with ports A,B,Y	Defined and instantiated as u1
Instance u1	Not exist	Created with port connections	Ready for simulation/use
Ports A,B,Y	Undefined	Connected to in1,in2,out	Connected and active

Key Moments - 3 Insights

Why do we use .A(in1) instead of just listing signals?

Using named port connections like .A(in1) clearly links the module port A to signal in1, avoiding mistakes from wrong order. See execution_table step 4.

Can we instantiate a module without naming ports?

Yes, by listing signals in order, but it is error-prone. Named connections are safer. This is implied in step 4.

What happens if port names don't match during instantiation?

The compiler will give an error because it can't connect signals properly. Step 4 shows correct naming is required.

Visual Quiz - 3 Questions

Look at the execution_table at step 4, what does .B(in2) mean?

A Assign in2 to output port B

B Create a new signal named B

C Connect module port B to signal in2

D Rename module AND2 to in2

💡 Hint

Refer to execution_table step 4 where ports are connected by name

At which step is the module AND2 fully defined?

A Step 1

B Step 3

C Step 4

D Step 5

💡 Hint

Check execution_table where 'endmodule' marks module definition end

If we change .Y(out) to .Y(result), what changes in variable_tracker?

A Port Y connects to signal result instead of out

B Instance u1 is deleted

C Module AND2 ports change

D No change at all

💡 Hint

Look at variable_tracker row for Ports A,B,Y and their connections

Concept Snapshot

Module instantiation syntax:
- Define module with ports
- Instantiate with: ModuleName instanceName(port connections);
- Connect ports by name: .port(signal)
- Named connections avoid order mistakes
- Instance acts like a reusable block in design

Full Transcript

This visual execution shows how a Verilog module is defined and instantiated. First, the module AND2 is defined with inputs A, B and output Y. Then, inside the module, output Y is assigned as the AND of inputs A and B. After the module ends, an instance named u1 is created by connecting signals in1, in2, and out to the module ports by name. This named connection ensures correct wiring. The instance u1 can then be used in simulation or synthesis as a 2-input AND gate. The execution table traces each step, and the variable tracker shows how the module and instance states change. Key moments clarify why named port connections are important and what happens if port names mismatch. The quiz tests understanding of port connections, module definition steps, and effects of changing port connections. This helps beginners see exactly how module instantiation works step-by-step.

Practice

1.

What is the main purpose of module instantiation in Verilog?

easy

A. To declare variables inside a module

B. To reuse and connect modules inside other modules

C. To write comments in the code

D. To define the clock frequency

Solution

1. Step 1: Understand module instantiation concept

   Module instantiation allows you to use one module inside another, making design reusable.

2. Step 2: Identify the correct purpose

   Among the options, only reusing and connecting modules matches the purpose of instantiation.

3. Final Answer:

   To reuse and connect modules inside other modules -> Option B

4. Quick Check:

   Module instantiation = reuse modules [OK]

Hint: Module instantiation = reuse modules inside others [OK]

Common Mistakes:

• Confusing instantiation with variable declaration
• Thinking instantiation is for comments
• Mixing instantiation with clock setup

2.

Which of the following is the correct syntax for instantiating a module named adder with ports a, b, and sum using named port connections?

module adder(input a, input b, output sum); ... endmodule

easy

A. adder my_adder(a, b, sum);

B. my_adder adder(.a(a), .b(b), .sum(sum));

C. adder(.a=a, .b=b, .sum=sum) my_adder;

D. adder my_adder(.a(a), .b(b), .sum(sum));

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot before port name and parentheses for signal, like .port(signal).

2. Step 2: Check instance name placement

   The instance name comes after the module name, so adder my_adder(...); is correct.

3. Final Answer:

   adder my_adder(.a(a), .b(b), .sum(sum)); -> Option D

4. Quick Check:

   ModuleName InstanceName(.port(signal)) [OK]

Hint: Instance name follows module name; use .port(signal) for named ports [OK]

Common Mistakes:

• Placing instance name before module name
• Using = instead of parentheses in port connections
• Omitting instance name

3.

Given the module and instantiation below, what is the value of out after simulation?

module inverter(input in, output out); assign out = ~in; endmodule

module top; reg a = 1'b0; wire b; inverter inv1(.in(a), .out(b)); endmodule

medium

A. b = 1'b1

B. b is undefined

C. Syntax error due to missing semicolon

D. b = 1'b0

Solution

1. Step 1: Understand inverter module behavior

   The inverter outputs the bitwise NOT of input in. If in is 0, output is 1.

2. Step 2: Check input value and connection

   Input a is initialized to 0, connected to inverter input in. So output b = ~0 = 1.

3. Final Answer:

   b = 1'b1 -> Option A

4. Quick Check:

   ~0 = 1, so output = 1 [OK]

Hint: Inverter flips input bit; 0 becomes 1 [OK]

Common Mistakes:

• Confusing input and output signals
• Assuming output equals input
• Missing initial value for input

4.

Identify the error in the following module instantiation:

module counter(input clk, output reg [3:0] count); ... endmodule

module top; wire clk; wire [3:0] cnt; counter cnt_inst(clk, cnt); counter cnt_inst(clk, cnt); endmodule

medium

A. Incorrect port connection order

B. Missing semicolon after module declaration

C. Duplicate instance name 'cnt_inst' used

D. Output port declared as wire instead of reg

Solution

1. Step 1: Check instance names in top module

   Two instances named cnt_inst are declared, which is not allowed.

2. Step 2: Verify other syntax elements

   Semicolons and port order appear correct; output port type mismatch is allowed since output is connected to wire.

3. Final Answer:

   Duplicate instance name 'cnt_inst' used -> Option C

4. Quick Check:

   Instance names must be unique [OK]

Hint: Each instance needs a unique name [OK]

Common Mistakes:

• Using same instance name twice
• Confusing port order with named connections
• Thinking output port must be reg in top

5.

You want to instantiate a module mux2to1 twice inside a top module, connecting inputs a, b, select sel, and outputs out1, out2. Which is the correct way to instantiate both with unique instance names and named port connections?

hard

A. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

B. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)), mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

C. mux2to1(.a(a), .b(b), .sel(sel), .out(out1)) mux1; mux2to1(.a(a), .b(b), .sel(sel), .out(out2)) mux2;

D. mux2to1 mux1(a, b, sel, out1); mux2to1 mux1(a, b, sel, out2);

Solution

1. Step 1: Confirm named port connection syntax

   Named ports use dot before port name and parentheses around signal, e.g., .a(a).

2. Step 2: Check instance names and separation

   Each instance must have a unique name and be separated by semicolons.

3. Step 3: Validate options

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); correctly names instances mux1 and mux2, uses named ports, and separates with semicolons.

4. Final Answer:

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); -> Option A

5. Quick Check:

   Unique instance names + named ports + semicolons = correct [OK]

Hint: Use unique instance names and semicolons between instantiations [OK]

Common Mistakes:

• Using same instance name twice
• Separating instances with commas instead of semicolons
• Placing instance name after port list