Module instantiation syntax in Verilog - Mini Project: Build & Apply

Module Instantiation Syntax in Verilog

📖 Scenario: You are designing a simple digital system using Verilog. You need to create a top-level module that uses a smaller module inside it. This is called module instantiation.Think of it like building a car (top module) that uses an engine (submodule). You will first create the engine module, then add it inside the car module.

🎯 Goal: Build a Verilog design with two modules: a submodule called adder and a top module called top_module. Instantiate the adder inside top_module using correct module instantiation syntax.

📋 What You'll Learn

Create a module named adder with inputs a, b and output sum.

Create a module named top_module with inputs x, y and output z.

Inside top_module, instantiate the adder module with instance name my_adder.

Connect x and y of top_module to a and b of adder respectively.

Connect output sum of adder to output z of top_module.

💡 Why This Matters

🌍 Real World

Module instantiation is the basic way to build complex digital circuits by combining smaller reusable blocks. This is how real chips and FPGA designs are structured.

💼 Career

Understanding module instantiation is essential for hardware engineers and FPGA developers to design and organize digital systems efficiently.

1

Create the adder module

Write a Verilog module named adder with inputs a and b (1-bit each) and output sum (1-bit). Inside the module, assign sum as the XOR of a and b.

Verilog

// Your code here

Hint

Use module keyword to start. Inputs and outputs are declared inside parentheses. Use assign to define sum as XOR of a and b.

2

Create the top_module with inputs and output

Write a Verilog module named top_module with inputs x and y (1-bit each) and output z (1-bit). Do not instantiate anything yet.

Verilog

module adder(input a, input b, output sum);
    assign sum = a ^ b;
endmodule

// Your code here

Hint

Use module keyword again. Declare inputs and output inside parentheses. Leave the body empty for now.

3

Instantiate adder inside top_module

Inside top_module, instantiate the adder module with instance name my_adder. Connect x to a, y to b, and z to sum using named port connections.

Verilog

module adder(input a, input b, output sum);
    assign sum = a ^ b;
endmodule

module top_module(input x, input y, output z);
    // Your code here
endmodule

Hint

Use the syntax: adder my_adder(.a(x), .b(y), .sum(z)); inside top_module.

4

Display the complete design

Print the entire Verilog code for both adder and top_module as your final output.

Verilog

module adder(input a, input b, output sum);
    assign sum = a ^ b;
endmodule

module top_module(input x, input y, output z);
    adder my_adder(.a(x), .b(y), .sum(z));
endmodule

// Your code here

Hint

Use $display statements to print the Verilog code lines exactly as written.

Practice

1.

What is the main purpose of module instantiation in Verilog?

easy

A. To declare variables inside a module

B. To reuse and connect modules inside other modules

C. To write comments in the code

D. To define the clock frequency

Solution

1. Step 1: Understand module instantiation concept

   Module instantiation allows you to use one module inside another, making design reusable.

2. Step 2: Identify the correct purpose

   Among the options, only reusing and connecting modules matches the purpose of instantiation.

3. Final Answer:

   To reuse and connect modules inside other modules -> Option B

4. Quick Check:

   Module instantiation = reuse modules [OK]

Hint: Module instantiation = reuse modules inside others [OK]

Common Mistakes:

• Confusing instantiation with variable declaration
• Thinking instantiation is for comments
• Mixing instantiation with clock setup

2.

Which of the following is the correct syntax for instantiating a module named adder with ports a, b, and sum using named port connections?

module adder(input a, input b, output sum); ... endmodule

easy

A. adder my_adder(a, b, sum);

B. my_adder adder(.a(a), .b(b), .sum(sum));

C. adder(.a=a, .b=b, .sum=sum) my_adder;

D. adder my_adder(.a(a), .b(b), .sum(sum));

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot before port name and parentheses for signal, like .port(signal).

2. Step 2: Check instance name placement

   The instance name comes after the module name, so adder my_adder(...); is correct.

3. Final Answer:

   adder my_adder(.a(a), .b(b), .sum(sum)); -> Option D

4. Quick Check:

   ModuleName InstanceName(.port(signal)) [OK]

Hint: Instance name follows module name; use .port(signal) for named ports [OK]

Common Mistakes:

• Placing instance name before module name
• Using = instead of parentheses in port connections
• Omitting instance name

3.

Given the module and instantiation below, what is the value of out after simulation?

module inverter(input in, output out); assign out = ~in; endmodule

module top; reg a = 1'b0; wire b; inverter inv1(.in(a), .out(b)); endmodule

medium

A. b = 1'b1

B. b is undefined

C. Syntax error due to missing semicolon

D. b = 1'b0

Solution

1. Step 1: Understand inverter module behavior

   The inverter outputs the bitwise NOT of input in. If in is 0, output is 1.

2. Step 2: Check input value and connection

   Input a is initialized to 0, connected to inverter input in. So output b = ~0 = 1.

3. Final Answer:

   b = 1'b1 -> Option A

4. Quick Check:

   ~0 = 1, so output = 1 [OK]

Hint: Inverter flips input bit; 0 becomes 1 [OK]

Common Mistakes:

• Confusing input and output signals
• Assuming output equals input
• Missing initial value for input

4.

Identify the error in the following module instantiation:

module counter(input clk, output reg [3:0] count); ... endmodule

module top; wire clk; wire [3:0] cnt; counter cnt_inst(clk, cnt); counter cnt_inst(clk, cnt); endmodule

medium

A. Incorrect port connection order

B. Missing semicolon after module declaration

C. Duplicate instance name 'cnt_inst' used

D. Output port declared as wire instead of reg

Solution

1. Step 1: Check instance names in top module

   Two instances named cnt_inst are declared, which is not allowed.

2. Step 2: Verify other syntax elements

   Semicolons and port order appear correct; output port type mismatch is allowed since output is connected to wire.

3. Final Answer:

   Duplicate instance name 'cnt_inst' used -> Option C

4. Quick Check:

   Instance names must be unique [OK]

Hint: Each instance needs a unique name [OK]

Common Mistakes:

• Using same instance name twice
• Confusing port order with named connections
• Thinking output port must be reg in top

5.

You want to instantiate a module mux2to1 twice inside a top module, connecting inputs a, b, select sel, and outputs out1, out2. Which is the correct way to instantiate both with unique instance names and named port connections?

hard

A. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

B. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)), mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

C. mux2to1(.a(a), .b(b), .sel(sel), .out(out1)) mux1; mux2to1(.a(a), .b(b), .sel(sel), .out(out2)) mux2;

D. mux2to1 mux1(a, b, sel, out1); mux2to1 mux1(a, b, sel, out2);

Solution

1. Step 1: Confirm named port connection syntax

   Named ports use dot before port name and parentheses around signal, e.g., .a(a).

2. Step 2: Check instance names and separation

   Each instance must have a unique name and be separated by semicolons.

3. Step 3: Validate options

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); correctly names instances mux1 and mux2, uses named ports, and separates with semicolons.

4. Final Answer:

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); -> Option A

5. Quick Check:

   Unique instance names + named ports + semicolons = correct [OK]

Hint: Use unique instance names and semicolons between instantiations [OK]

Common Mistakes:

• Using same instance name twice
• Separating instances with commas instead of semicolons
• Placing instance name after port list