Module instantiation syntax in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of simple module instantiation

What is the output of the following Verilog code when simulated?

Verilog

module adder(input wire a, input wire b, output wire sum);
  assign sum = a ^ b;
endmodule

module top;
  reg x = 1'b0;
  reg y = 1'b1;
  wire s;

  adder my_adder(.a(x), .b(y), .sum(s));

  initial begin
    $display("Sum = %b", s);
  end
endmodule

A Sum = 1

B Sum = 0

C Sum = x

D Simulation error

💡 Hint

Think about the XOR operation between inputs 0 and 1.

The module adder computes the XOR of inputs a and b. Since a=0 and b=1, the output sum is 1.

❓ Predict Output

intermediate

Output with positional module instantiation

What will be printed when this Verilog code runs?

Verilog

module inverter(input wire in, output wire out);
  assign out = ~in;
endmodule

module top;
  reg a = 1'b1;
  wire b;

  inverter inv1(a, b);

  initial begin
    $display("Output = %b", b);
  end
endmodule

A Output = x

B Output = 0

C Output = 1

D Compilation error

💡 Hint

Remember that ~ is bitwise NOT.

The inverter module outputs the bitwise NOT of input a. Since a=1, output b is 0.

🔧 Debug

advanced

Identify the syntax error in module instantiation

Which option contains a syntax error in the module instantiation?

Verilog

module multiplier(input wire [1:0] a, input wire [1:0] b, output wire [3:0] product);
  assign product = a * b;
endmodule

module top;
  reg [1:0] x = 2'b10;
  reg [1:0] y = 2'b11;
  wire [3:0] p;

  // Instantiations below
  // Choose the one with syntax error
endmodule

A multiplier m3(.a = x, .b = y, .product = p);

B multiplier m2(x, y, p);

C multiplier m1(.a(x), .b(y), .product(p));

D multiplier m4(.a(x), .b(y), product(p));

💡 Hint

Check the correct syntax for named port connections.

In Verilog, named port connections use the syntax .port(signal) without equals sign. Option A uses = which is invalid.

❓ Predict Output

advanced

Value of output after multiple instantiations

What is the value of out after simulation?

Verilog

module and_gate(input wire a, input wire b, output wire out);
  assign out = a & b;
endmodule

module top;
  reg p = 1'b1;
  reg q = 1'b0;
  wire r, s, out;

  and_gate g1(.a(p), .b(q), .out(r));
  and_gate g2(.a(p), .b(p), .out(s));
  and_gate g3(.a(r), .b(s), .out(out));

  initial begin
    $display("Final output = %b", out);
  end
endmodule

A Simulation error

B Final output = 1

C Final output = x

D Final output = 0

💡 Hint

Trace the AND operations step by step.

First gate: r = p & q = 1 & 0 = 0
Second gate: s = p & p = 1 & 1 = 1
Third gate: out = r & s = 0 & 1 = 0

🧠 Conceptual

expert

Understanding hierarchical module instantiation

Consider a top-level module instantiating two submodules. Which statement is true about the connections?

A Only positional port mapping is allowed for hierarchical connections.

B Submodules can directly access internal signals of the top module without port connections.

C Signals declared in the top module can be connected to submodules using named port mapping.

D Module instantiation requires all signals to be global to connect properly.

💡 Hint

Think about how modules communicate in Verilog.

In Verilog, submodules communicate with the top module through ports. Named port mapping is a clear way to connect signals declared in the top module to submodules. Submodules cannot access internal signals of the top module directly without ports. Signals do not need to be global. Both named and positional mappings are allowed.

Practice

1.

What is the main purpose of module instantiation in Verilog?

easy

A. To declare variables inside a module

B. To reuse and connect modules inside other modules

C. To write comments in the code

D. To define the clock frequency

Solution

1. Step 1: Understand module instantiation concept

   Module instantiation allows you to use one module inside another, making design reusable.

2. Step 2: Identify the correct purpose

   Among the options, only reusing and connecting modules matches the purpose of instantiation.

3. Final Answer:

   To reuse and connect modules inside other modules -> Option B

4. Quick Check:

   Module instantiation = reuse modules [OK]

Hint: Module instantiation = reuse modules inside others [OK]

Common Mistakes:

• Confusing instantiation with variable declaration
• Thinking instantiation is for comments
• Mixing instantiation with clock setup

2.

Which of the following is the correct syntax for instantiating a module named adder with ports a, b, and sum using named port connections?

module adder(input a, input b, output sum); ... endmodule

easy

A. adder my_adder(a, b, sum);

B. my_adder adder(.a(a), .b(b), .sum(sum));

C. adder(.a=a, .b=b, .sum=sum) my_adder;

D. adder my_adder(.a(a), .b(b), .sum(sum));

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot before port name and parentheses for signal, like .port(signal).

2. Step 2: Check instance name placement

   The instance name comes after the module name, so adder my_adder(...); is correct.

3. Final Answer:

   adder my_adder(.a(a), .b(b), .sum(sum)); -> Option D

4. Quick Check:

   ModuleName InstanceName(.port(signal)) [OK]

Hint: Instance name follows module name; use .port(signal) for named ports [OK]

Common Mistakes:

• Placing instance name before module name
• Using = instead of parentheses in port connections
• Omitting instance name

3.

Given the module and instantiation below, what is the value of out after simulation?

module inverter(input in, output out); assign out = ~in; endmodule

module top; reg a = 1'b0; wire b; inverter inv1(.in(a), .out(b)); endmodule

medium

A. b = 1'b1

B. b is undefined

C. Syntax error due to missing semicolon

D. b = 1'b0

Solution

1. Step 1: Understand inverter module behavior

   The inverter outputs the bitwise NOT of input in. If in is 0, output is 1.

2. Step 2: Check input value and connection

   Input a is initialized to 0, connected to inverter input in. So output b = ~0 = 1.

3. Final Answer:

   b = 1'b1 -> Option A

4. Quick Check:

   ~0 = 1, so output = 1 [OK]

Hint: Inverter flips input bit; 0 becomes 1 [OK]

Common Mistakes:

• Confusing input and output signals
• Assuming output equals input
• Missing initial value for input

4.

Identify the error in the following module instantiation:

module counter(input clk, output reg [3:0] count); ... endmodule

module top; wire clk; wire [3:0] cnt; counter cnt_inst(clk, cnt); counter cnt_inst(clk, cnt); endmodule

medium

A. Incorrect port connection order

B. Missing semicolon after module declaration

C. Duplicate instance name 'cnt_inst' used

D. Output port declared as wire instead of reg

Solution

1. Step 1: Check instance names in top module

   Two instances named cnt_inst are declared, which is not allowed.

2. Step 2: Verify other syntax elements

   Semicolons and port order appear correct; output port type mismatch is allowed since output is connected to wire.

3. Final Answer:

   Duplicate instance name 'cnt_inst' used -> Option C

4. Quick Check:

   Instance names must be unique [OK]

Hint: Each instance needs a unique name [OK]

Common Mistakes:

• Using same instance name twice
• Confusing port order with named connections
• Thinking output port must be reg in top

5.

You want to instantiate a module mux2to1 twice inside a top module, connecting inputs a, b, select sel, and outputs out1, out2. Which is the correct way to instantiate both with unique instance names and named port connections?

hard

A. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

B. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)), mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

C. mux2to1(.a(a), .b(b), .sel(sel), .out(out1)) mux1; mux2to1(.a(a), .b(b), .sel(sel), .out(out2)) mux2;

D. mux2to1 mux1(a, b, sel, out1); mux2to1 mux1(a, b, sel, out2);

Solution

1. Step 1: Confirm named port connection syntax

   Named ports use dot before port name and parentheses around signal, e.g., .a(a).

2. Step 2: Check instance names and separation

   Each instance must have a unique name and be separated by semicolons.

3. Step 3: Validate options

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); correctly names instances mux1 and mux2, uses named ports, and separates with semicolons.

4. Final Answer:

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); -> Option A

5. Quick Check:

   Unique instance names + named ports + semicolons = correct [OK]

Hint: Use unique instance names and semicolons between instantiations [OK]

Common Mistakes:

• Using same instance name twice
• Separating instances with commas instead of semicolons
• Placing instance name after port list