Module instantiation syntax in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the purpose of module instantiation in Verilog?

Module instantiation allows you to create an instance of a module inside another module, enabling reuse and hierarchical design.

beginner

How do you instantiate a module using positional port mapping?

You list the module name, instance name, and then connect ports in the order they are declared in the module using parentheses and commas.

intermediate

What is the difference between positional and named port mapping in module instantiation?

Positional mapping connects ports by order, while named mapping connects ports by explicitly naming each port, improving clarity and reducing errors.

beginner

Write the syntax for named port mapping in Verilog module instantiation.

module_name instance_name (.port1(signal1), .port2(signal2), ...);

intermediate

Why is named port mapping preferred in complex designs?

Because it clearly shows which signal connects to which port, making the code easier to read and less prone to mistakes when ports change order.

Which of the following is the correct way to instantiate a module named 'adder' with ports a, b, and sum using positional mapping?

A adder (a=x, b=y, sum=z);

B adder my_adder (x, y, z);

C my_adder adder (x, y, z);

D adder my_adder (.a=x, .b=y, .sum=z);

In positional mapping, the instance name follows the module name, then ports are connected in order without naming.

What symbol is used to connect a port to a signal in named port mapping?

A :

B =

C ->

D .

Named port mapping uses a dot (.) before the port name, like .port(signal).

Which is a benefit of using named port mapping over positional mapping?

A Allows ports to be connected in any order

B Requires less typing

C Only works with modules with few ports

D Is faster to simulate

Named port mapping lets you connect ports in any order by explicitly naming them.

In Verilog, what is the correct order of elements in a module instantiation statement?

A Instance name, module name, port connections

B Port connections, instance name, module name

C Module name, instance name, port connections

D Port connections, module name, instance name

The syntax is: module_name instance_name (port connections);

Which of these is NOT a valid reason to use module instantiation?

A Increase code duplication

B Create hierarchical designs

C Reuse code

D Organize complex circuits

Module instantiation helps reduce code duplication, not increase it.

Explain how to instantiate a module in Verilog using named port mapping.

Think about how you clearly connect each port to a signal by name.

Describe the advantages of using module instantiation in hardware design.

Consider how building blocks help organize complex projects.

Practice

1.

What is the main purpose of module instantiation in Verilog?

easy

A. To declare variables inside a module

B. To reuse and connect modules inside other modules

C. To write comments in the code

D. To define the clock frequency

Solution

1. Step 1: Understand module instantiation concept

   Module instantiation allows you to use one module inside another, making design reusable.

2. Step 2: Identify the correct purpose

   Among the options, only reusing and connecting modules matches the purpose of instantiation.

3. Final Answer:

   To reuse and connect modules inside other modules -> Option B

4. Quick Check:

   Module instantiation = reuse modules [OK]

Hint: Module instantiation = reuse modules inside others [OK]

Common Mistakes:

• Confusing instantiation with variable declaration
• Thinking instantiation is for comments
• Mixing instantiation with clock setup

2.

Which of the following is the correct syntax for instantiating a module named adder with ports a, b, and sum using named port connections?

module adder(input a, input b, output sum); ... endmodule

easy

A. adder my_adder(a, b, sum);

B. my_adder adder(.a(a), .b(b), .sum(sum));

C. adder(.a=a, .b=b, .sum=sum) my_adder;

D. adder my_adder(.a(a), .b(b), .sum(sum));

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot before port name and parentheses for signal, like .port(signal).

2. Step 2: Check instance name placement

   The instance name comes after the module name, so adder my_adder(...); is correct.

3. Final Answer:

   adder my_adder(.a(a), .b(b), .sum(sum)); -> Option D

4. Quick Check:

   ModuleName InstanceName(.port(signal)) [OK]

Hint: Instance name follows module name; use .port(signal) for named ports [OK]

Common Mistakes:

• Placing instance name before module name
• Using = instead of parentheses in port connections
• Omitting instance name

3.

Given the module and instantiation below, what is the value of out after simulation?

module inverter(input in, output out); assign out = ~in; endmodule

module top; reg a = 1'b0; wire b; inverter inv1(.in(a), .out(b)); endmodule

medium

A. b = 1'b1

B. b is undefined

C. Syntax error due to missing semicolon

D. b = 1'b0

Solution

1. Step 1: Understand inverter module behavior

   The inverter outputs the bitwise NOT of input in. If in is 0, output is 1.

2. Step 2: Check input value and connection

   Input a is initialized to 0, connected to inverter input in. So output b = ~0 = 1.

3. Final Answer:

   b = 1'b1 -> Option A

4. Quick Check:

   ~0 = 1, so output = 1 [OK]

Hint: Inverter flips input bit; 0 becomes 1 [OK]

Common Mistakes:

• Confusing input and output signals
• Assuming output equals input
• Missing initial value for input

4.

Identify the error in the following module instantiation:

module counter(input clk, output reg [3:0] count); ... endmodule

module top; wire clk; wire [3:0] cnt; counter cnt_inst(clk, cnt); counter cnt_inst(clk, cnt); endmodule

medium

A. Incorrect port connection order

B. Missing semicolon after module declaration

C. Duplicate instance name 'cnt_inst' used

D. Output port declared as wire instead of reg

Solution

1. Step 1: Check instance names in top module

   Two instances named cnt_inst are declared, which is not allowed.

2. Step 2: Verify other syntax elements

   Semicolons and port order appear correct; output port type mismatch is allowed since output is connected to wire.

3. Final Answer:

   Duplicate instance name 'cnt_inst' used -> Option C

4. Quick Check:

   Instance names must be unique [OK]

Hint: Each instance needs a unique name [OK]

Common Mistakes:

• Using same instance name twice
• Confusing port order with named connections
• Thinking output port must be reg in top

5.

You want to instantiate a module mux2to1 twice inside a top module, connecting inputs a, b, select sel, and outputs out1, out2. Which is the correct way to instantiate both with unique instance names and named port connections?

hard

A. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

B. mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)), mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2));

C. mux2to1(.a(a), .b(b), .sel(sel), .out(out1)) mux1; mux2to1(.a(a), .b(b), .sel(sel), .out(out2)) mux2;

D. mux2to1 mux1(a, b, sel, out1); mux2to1 mux1(a, b, sel, out2);

Solution

1. Step 1: Confirm named port connection syntax

   Named ports use dot before port name and parentheses around signal, e.g., .a(a).

2. Step 2: Check instance names and separation

   Each instance must have a unique name and be separated by semicolons.

3. Step 3: Validate options

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); correctly names instances mux1 and mux2, uses named ports, and separates with semicolons.

4. Final Answer:

   mux2to1 mux1(.a(a), .b(b), .sel(sel), .out(out1)); mux2to1 mux2(.a(a), .b(b), .sel(sel), .out(out2)); -> Option A

5. Quick Check:

   Unique instance names + named ports + semicolons = correct [OK]

Hint: Use unique instance names and semicolons between instantiations [OK]

Common Mistakes:

• Using same instance name twice
• Separating instances with commas instead of semicolons
• Placing instance name after port list