Metastability and synchronizer design in Verilog - Step-by-Step Execution

Concept Flow - Metastability and synchronizer design

Input signal arrives asynchronously

↓

Flip-flop samples input

↓

Metastability possible?

No→Output stable

Yes↓

Flip-flop output unstable (metastable)

↓

Wait for resolution time

↓

Output stabilizes

↓

Pass to next flip-flop (synchronizer stage)

↓

Output synchronized and stable

The input signal is sampled asynchronously by flip-flops. If metastability occurs, the output may be unstable temporarily. Additional flip-flop stages allow time for the signal to stabilize before use.

Execution Sample

Verilog

module synchronizer(input async_in, input clk, output reg sync_out);
  reg ff1;
  always @(posedge clk) ff1 <= async_in;
  always @(posedge clk) sync_out <= ff1;
endmodule

A 2-stage synchronizer that samples an asynchronous input and outputs a stable synchronized signal.

Execution Table

Step	clk edge	async_in	ff1 (stage 1)	sync_out (stage 2)	Metastability?
1	rising	0	0	0	No
2	rising	1	1 (may be metastable)	0	Possible
3	rising	1	1 (stable)	1 (may be metastable)	Possible
4	rising	1	1 (stable)	1 (stable)	No
5	rising	0	0	1 (stable)	No
6	rising	0	0	0 (stable)	No

💡 After two clock cycles, output sync_out stabilizes reflecting async_in value.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	Final
async_in	0	1	1	1	1	0
ff1	0	1 (may be metastable)	1 (stable)	1 (stable)	1 (stable)	0
sync_out	0	0	1 (may be metastable)	1 (stable)	1 (stable)	0 (stable)

Key Moments - 3 Insights

Why can ff1 output be metastable at step 2?

Because async_in changes close to the clock edge, the flip-flop may not settle immediately, causing metastability as shown in execution_table row 2.

Why do we use two flip-flops in the synchronizer?

The first flip-flop may become metastable, but the second flip-flop samples its output on the next clock edge, allowing metastability to resolve before sync_out is used (rows 3 and 4).

What happens if we use only one flip-flop?

Metastability might propagate to output without time to resolve, risking unstable output signals.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of ff1 at step 2?

A 1 (stable)

B 0

C 1 (may be metastable)

D Unknown

💡 Hint

Check the 'ff1 (stage 1)' column at step 2 in execution_table.

At which step does sync_out become stable after async_in changes to 1?

A Step 2

B Step 4

C Step 3

D Step 5

💡 Hint

Look at 'sync_out (stage 2)' column and metastability status in execution_table rows 3 and 4.

If we add a third flip-flop stage, how would the variable_tracker for sync_out change?

A It would stabilize one clock cycle later

B It would stabilize earlier

C It would never stabilize

D No change

💡 Hint

More stages give more time for metastability to resolve, so output stabilizes later (see variable_tracker pattern).

Concept Snapshot

Metastability occurs when asynchronous signals are sampled by flip-flops.
Use multiple flip-flop stages (synchronizer) to reduce metastability risk.
Each stage samples the previous output on clock edges.
Output stabilizes after passing through all stages.
This design improves reliability in clock domain crossing.

Full Transcript

Metastability happens when a flip-flop samples an input that changes near the clock edge, causing temporary unstable output. To handle this, we use a synchronizer with two or more flip-flops in series. The first flip-flop may become metastable, but the next flip-flop samples its output on the next clock cycle, giving time for the signal to stabilize. This reduces the chance of unstable signals propagating. The example Verilog code shows a 2-stage synchronizer. The execution table traces how the input async_in is sampled by ff1 and then sync_out, showing possible metastability and eventual stabilization. Variable tracking shows how values change step-by-step. Key moments clarify why metastability occurs and why multiple stages help. The quiz tests understanding of these steps. This method is essential for reliable clock domain crossing in digital designs.

Practice

1. What is the main purpose of a synchronizer in Verilog designs?

easy

A. To generate reset signals for flip-flops

B. To reduce metastability by allowing signals to settle before use

C. To convert analog signals to digital

D. To increase clock frequency for faster operation

Solution

1. Step 1: Understand metastability

   Metastability occurs when signals change close to clock edges, causing uncertain outputs.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to give signals time to stabilize and avoid metastability effects.

3. Final Answer:

   To reduce metastability by allowing signals to settle before use -> Option B

4. Quick Check:

   Synchronizer purpose = reduce metastability [OK]

Hint: Synchronizers help signals settle before use to avoid errors [OK]

Common Mistakes:

• Thinking synchronizers speed up clocks
• Confusing synchronizers with reset generators
• Assuming synchronizers convert signal types

2. Which Verilog code snippet correctly implements a 2-stage synchronizer for an asynchronous input async_in?

easy

A. reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end

B. reg sync1; always @(negedge clk) sync1 <= async_in;

C. wire sync1 = async_in; wire sync2 = sync1;

D. reg sync1, sync2; always @(posedge clk) begin sync2 <= async_in; sync1 <= sync2; end

Solution

1. Step 1: Identify correct synchronizer structure

   A 2-stage synchronizer uses two flip-flops in series clocked by the same clock.

2. Step 2: Check code correctness

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end correctly assigns sync1 first, then sync2 on the clock's rising edge, matching the synchronizer design.

3. Final Answer:

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end -> Option A

4. Quick Check:

   Two flip-flops in series = reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end [OK]

Hint: Synchronizer uses two flip-flops clocked on posedge [OK]

Common Mistakes:

• Using negedge clock instead of posedge
• Assigning signals in wrong order
• Using wires instead of regs for flip-flops

3. Given the following Verilog code, what is the output value of sync_out after two clock cycles if async_in changes from 0 to 1 just before the first clock edge?

reg sync1, sync2;
always @(posedge clk) begin
  sync1 <= async_in;
  sync2 <= sync1;
end
assign sync_out = sync2;

medium

A. sync_out becomes 1 after two clock cycles

B. sync_out becomes 1 immediately at first clock edge

C. sync_out remains 0 indefinitely

D. sync_out toggles between 0 and 1 every clock

Solution

1. Step 1: Trace signal through synchronizer stages

   At first clock edge, sync1 captures async_in=1, but sync2 still holds old sync1 value (0).

2. Step 2: After second clock edge

   At second clock edge, sync2 captures sync1=1, so sync_out becomes 1.

3. Final Answer:

   sync_out becomes 1 after two clock cycles -> Option A

4. Quick Check:

   Two flip-flop delay = output after two clocks [OK]

Hint: Synchronizer output updates after two clock cycles [OK]

Common Mistakes:

• Assuming output changes immediately
• Ignoring flip-flop delay stages
• Confusing sync1 and sync2 roles

4. Identify the error in this synchronizer code snippet:

reg sync1, sync2;
always @(posedge clk) begin
  sync2 <= async_in;
  sync1 <= sync2;
end

medium

A. Clock edge should be negedge instead of posedge

B. Missing asynchronous reset signal

C. Using blocking assignments instead of non-blocking

D. The flip-flop assignments are reversed; sync1 should capture async_in first

Solution

1. Step 1: Analyze assignment order

   The first flip-flop should capture async_in, then the second captures the first flip-flop's output.

2. Step 2: Identify reversed assignments

   Here, sync2 captures async_in first, which is incorrect; sync1 should capture async_in first.

3. Final Answer:

   The flip-flop assignments are reversed; sync1 should capture async_in first -> Option D

4. Quick Check:

   Correct order: sync1 <= async_in; sync2 <= sync1 [OK]

Hint: First flip-flop captures async input, second captures first flip-flop [OK]

Common Mistakes:

• Swapping flip-flop assignment order
• Forgetting non-blocking assignments
• Assuming reset is mandatory for synchronizers

5. You need to design a synchronizer for a signal coming from a different clock domain that toggles very fast. Which approach best reduces metastability risk and ensures stable output?

hard

A. Use combinational logic to directly sample the asynchronous signal

B. Use a single flip-flop synchronizer with asynchronous reset

C. Use a 3-stage synchronizer with flip-flops clocked by the receiving clock

D. Use a 2-stage synchronizer clocked by the source clock

Solution

1. Step 1: Understand metastability risk with fast toggling signals

   Fast toggling signals crossing clock domains increase metastability risk; more synchronization stages help reduce it.

2. Step 2: Choose proper synchronizer design

   A 3-stage synchronizer clocked by the receiving clock provides more settling time and reduces metastability better than fewer stages or wrong clock domains.

3. Final Answer:

   Use a 3-stage synchronizer with flip-flops clocked by the receiving clock -> Option C

4. Quick Check:

   More stages + receiving clock = better metastability reduction [OK]

Hint: More flip-flop stages reduce metastability risk [OK]

Common Mistakes:

• Using source clock instead of receiving clock
• Using too few synchronizer stages
• Sampling asynchronously with combinational logic