Metastability and synchronizer design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple 2-flip-flop synchronizer

Consider this Verilog code for a 2-flip-flop synchronizer. What is the output value of sync_out after 3 clock cycles if the asynchronous input async_in is held high from the start?

module sync(input clk, input async_in, output reg sync_out);
  reg ff1;
  always @(posedge clk) begin
    ff1 <= async_in;
    sync_out <= ff1;
  end
endmodule

Verilog

module sync(input clk, input async_in, output reg sync_out);
  reg ff1;
  always @(posedge clk) begin
    ff1 <= async_in;
    sync_out <= ff1;
  end
endmodule

A sync_out is 0 after 3 clock cycles

B sync_out is 1 after 3 clock cycles

C sync_out remains undefined (X) after 3 clock cycles

D sync_out toggles between 0 and 1 every clock cycle

💡 Hint

Think about how the input propagates through two flip-flops on each clock edge.

The first flip-flop captures the async input on the first clock edge, and the second flip-flop captures the output of the first on the next clock edge. After 2 clock cycles, sync_out will reflect the stable input value 1.

🧠 Conceptual

intermediate

Cause of metastability in synchronizers

What is the primary cause of metastability in a flip-flop synchronizer circuit?

A Input signal changes exactly at the clock edge violating setup time

B Flip-flop power supply voltage fluctuations

C Using asynchronous reset signals

D Clock frequency being too low

💡 Hint

Metastability happens when timing requirements are violated at the flip-flop input.

Metastability occurs when the input changes close to the clock edge, violating the setup or hold time, causing the flip-flop output to become unpredictable temporarily.

🔧 Debug

advanced

Identify the bug causing metastability risk

This Verilog code attempts to synchronize an asynchronous input but still risks metastability. What is the bug?

module sync_bug(input clk, input async_in, output reg sync_out);
  reg ff;
  always @(posedge clk) begin
    ff <= async_in;
    sync_out <= async_in;
  end
endmodule

Verilog

module sync_bug(input clk, input async_in, output reg sync_out);
  reg ff;
  always @(posedge clk) begin
    ff <= async_in;
    sync_out <= async_in;
  end
endmodule

A sync_out is assigned directly from async_in instead of from ff

B Missing asynchronous reset signal

C ff register is not initialized

D Using blocking assignments instead of non-blocking

💡 Hint

Check which signal sync_out depends on inside the clocked block.

sync_out should be assigned from the synchronized register ff, not directly from async_in, to reduce metastability risk.

📝 Syntax

advanced

Syntax error in synchronizer module

Which option contains a syntax error in this synchronizer Verilog code snippet?

module sync(input clk, input async_in, output reg sync_out);
  reg ff1, ff2;
  always @(posedge clk) begin
    ff1 <= async_in;
    ff2 <= ff1;
    sync_out <= ff2;
  end
endmodule

A

module sync(input clk, input async_in, output reg sync_out);
  reg ff1, ff2;
  always @(posedge clk) begin
    ff1 <= async_in;
    ff2 <= ff1;
    sync_out <= ff2
  end
endmodule

B

module sync(input clk, input async_in, output reg sync_out);
  reg ff1, ff2;
  always @(posedge clk) begin
    ff1 <= async_in;
    ff2 <= ff1;
    sync_out <= ff2;
  end
endmodule

C

module sync(input clk, input async_in, output reg sync_out)
  reg ff1, ff2;
  always @(posedge clk) begin
    ff1 <= async_in;
    ff2 <= ff1;
    sync_out <= ff2;
  end
endmodule

D

module sync(input clk, input async_in, output reg sync_out);
  reg ff1, ff2;
  always @(posedge clk) begin
    ff1 = async_in;
    ff2 = ff1;
    sync_out = ff2;
  end
endmodule

💡 Hint

Check for missing punctuation or keywords in module declaration.

Option C is missing a semicolon after the module declaration line, causing a syntax error.

🚀 Application

expert

Calculate Mean Time Between Failures (MTBF) for synchronizer

Given a synchronizer with a clock frequency of 100 MHz, a resolution time constant (tau) of 0.1 ns, and a setup time window (Tsetup) of 0.5 ns, what is the approximate MTBF in seconds? Use the formula:

MTBF = exp(Tsetup / tau) / (clock_freq * Tsetup)

Choose the closest value.

A Approximately 3.68e+04 seconds

B Approximately 5.43e+08 seconds

C Approximately 1.48e+06 seconds

D Approximately 2.71e+03 seconds

💡 Hint

Calculate exp(0.5/0.1) = exp(5) first, then divide by (100e6 * 0.5e-9).

exp(5) ≈ 148.41; clock_freq * Tsetup = 100e6 * 0.5e-9 = 0.05; MTBF ≈ 148.41 / 0.05 = 2968.2 seconds. Rechecking calculation: Actually, clock_freq * Tsetup = 100e6 * 0.5e-9 = 0.05, so MTBF = 148.41 / 0.05 = 2968.2 seconds. The closest option is A (1.48e+06) is incorrect, correct is about 2.97e+03 seconds. So option D is correct. Adjusting answer accordingly.

Practice

1. What is the main purpose of a synchronizer in Verilog designs?

easy

A. To generate reset signals for flip-flops

B. To reduce metastability by allowing signals to settle before use

C. To convert analog signals to digital

D. To increase clock frequency for faster operation

Solution

1. Step 1: Understand metastability

   Metastability occurs when signals change close to clock edges, causing uncertain outputs.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to give signals time to stabilize and avoid metastability effects.

3. Final Answer:

   To reduce metastability by allowing signals to settle before use -> Option B

4. Quick Check:

   Synchronizer purpose = reduce metastability [OK]

Hint: Synchronizers help signals settle before use to avoid errors [OK]

Common Mistakes:

• Thinking synchronizers speed up clocks
• Confusing synchronizers with reset generators
• Assuming synchronizers convert signal types

2. Which Verilog code snippet correctly implements a 2-stage synchronizer for an asynchronous input async_in?

easy

A. reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end

B. reg sync1; always @(negedge clk) sync1 <= async_in;

C. wire sync1 = async_in; wire sync2 = sync1;

D. reg sync1, sync2; always @(posedge clk) begin sync2 <= async_in; sync1 <= sync2; end

Solution

1. Step 1: Identify correct synchronizer structure

   A 2-stage synchronizer uses two flip-flops in series clocked by the same clock.

2. Step 2: Check code correctness

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end correctly assigns sync1 first, then sync2 on the clock's rising edge, matching the synchronizer design.

3. Final Answer:

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end -> Option A

4. Quick Check:

   Two flip-flops in series = reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end [OK]

Hint: Synchronizer uses two flip-flops clocked on posedge [OK]

Common Mistakes:

• Using negedge clock instead of posedge
• Assigning signals in wrong order
• Using wires instead of regs for flip-flops

3. Given the following Verilog code, what is the output value of sync_out after two clock cycles if async_in changes from 0 to 1 just before the first clock edge?

reg sync1, sync2;
always @(posedge clk) begin
  sync1 <= async_in;
  sync2 <= sync1;
end
assign sync_out = sync2;

medium

A. sync_out becomes 1 after two clock cycles

B. sync_out becomes 1 immediately at first clock edge

C. sync_out remains 0 indefinitely

D. sync_out toggles between 0 and 1 every clock

Solution

1. Step 1: Trace signal through synchronizer stages

   At first clock edge, sync1 captures async_in=1, but sync2 still holds old sync1 value (0).

2. Step 2: After second clock edge

   At second clock edge, sync2 captures sync1=1, so sync_out becomes 1.

3. Final Answer:

   sync_out becomes 1 after two clock cycles -> Option A

4. Quick Check:

   Two flip-flop delay = output after two clocks [OK]

Hint: Synchronizer output updates after two clock cycles [OK]

Common Mistakes:

• Assuming output changes immediately
• Ignoring flip-flop delay stages
• Confusing sync1 and sync2 roles

4. Identify the error in this synchronizer code snippet:

reg sync1, sync2;
always @(posedge clk) begin
  sync2 <= async_in;
  sync1 <= sync2;
end

medium

A. Clock edge should be negedge instead of posedge

B. Missing asynchronous reset signal

C. Using blocking assignments instead of non-blocking

D. The flip-flop assignments are reversed; sync1 should capture async_in first

Solution

1. Step 1: Analyze assignment order

   The first flip-flop should capture async_in, then the second captures the first flip-flop's output.

2. Step 2: Identify reversed assignments

   Here, sync2 captures async_in first, which is incorrect; sync1 should capture async_in first.

3. Final Answer:

   The flip-flop assignments are reversed; sync1 should capture async_in first -> Option D

4. Quick Check:

   Correct order: sync1 <= async_in; sync2 <= sync1 [OK]

Hint: First flip-flop captures async input, second captures first flip-flop [OK]

Common Mistakes:

• Swapping flip-flop assignment order
• Forgetting non-blocking assignments
• Assuming reset is mandatory for synchronizers

5. You need to design a synchronizer for a signal coming from a different clock domain that toggles very fast. Which approach best reduces metastability risk and ensures stable output?

hard

A. Use combinational logic to directly sample the asynchronous signal

B. Use a single flip-flop synchronizer with asynchronous reset

C. Use a 3-stage synchronizer with flip-flops clocked by the receiving clock

D. Use a 2-stage synchronizer clocked by the source clock

Solution

1. Step 1: Understand metastability risk with fast toggling signals

   Fast toggling signals crossing clock domains increase metastability risk; more synchronization stages help reduce it.

2. Step 2: Choose proper synchronizer design

   A 3-stage synchronizer clocked by the receiving clock provides more settling time and reduces metastability better than fewer stages or wrong clock domains.

3. Final Answer:

   Use a 3-stage synchronizer with flip-flops clocked by the receiving clock -> Option C

4. Quick Check:

   More stages + receiving clock = better metastability reduction [OK]

Hint: More flip-flop stages reduce metastability risk [OK]

Common Mistakes:

• Using source clock instead of receiving clock
• Using too few synchronizer stages
• Sampling asynchronously with combinational logic