Metastability and synchronizer design in Verilog - Mini Project: Build & Apply

Metastability and Synchronizer Design in Verilog

📖 Scenario: In digital circuits, signals crossing between different clock domains can cause unpredictable behavior called metastability. To avoid this, engineers use synchronizers--small circuits that help signals settle safely before use.In this project, you will build a simple 2-flip-flop synchronizer in Verilog to safely transfer a signal from an asynchronous input to a clocked domain.

🎯 Goal: You will create a Verilog module that implements a 2-stage synchronizer for an asynchronous input signal. This synchronizer will reduce the risk of metastability by passing the input through two flip-flops clocked by the destination clock.

📋 What You'll Learn

Create a Verilog module named synchronizer with inputs clk and async_in, and output sync_out.

Declare two internal registers sync_ff1 and sync_ff2 to hold intermediate states.

On every rising edge of clk, assign sync_ff1 the value of async_in, and sync_ff2 the value of sync_ff1.

Assign sync_out the value of sync_ff2.

Print the synchronized output signal.

💡 Why This Matters

🌍 Real World

Synchronizers are used in almost all digital systems where signals cross between different clock domains, such as in microprocessors, communication interfaces, and FPGA designs.

💼 Career

Understanding and designing synchronizers is essential for hardware engineers working on reliable digital circuit designs to prevent timing errors and system failures.

1

Create the module and declare inputs and outputs

Write a Verilog module named synchronizer with inputs clk and async_in, and output sync_out. Declare sync_out as a reg type.

Verilog

module synchronizer(input clk, input async_in, output reg sync_out);
// Your code here
endmodule

Hint

Start by defining the module and its ports exactly as described.

2

Declare two internal registers for synchronization

Inside the synchronizer module, declare two registers named sync_ff1 and sync_ff2.

Verilog

module synchronizer(input clk, input async_in, output reg sync_out);
reg sync_ff1;
reg sync_ff2;
// Your code here
endmodule

Hint

Declare two registers to hold the intermediate flip-flop states.

3

Implement the 2-stage synchronizer logic

Add an always block triggered on the rising edge of clk. Inside it, assign sync_ff1 the value of async_in, then assign sync_ff2 the value of sync_ff1. Finally, assign sync_out the value of sync_ff2.

Verilog

module synchronizer(input clk, input async_in, output reg sync_out);
reg sync_ff1;
reg sync_ff2;

always @(posedge clk) begin
    // Your code here
end

endmodule

Hint

Use non-blocking assignments (<=) inside the always block to update registers on clock edge.

4

Print the synchronized output signal

Write a testbench code snippet that instantiates the synchronizer module and prints the value of sync_out after some clock cycles. Use $display to show the synchronized output.

Verilog

module testbench;
reg clk = 0;
reg async_in = 0;
wire sync_out;

synchronizer uut(.clk(clk), .async_in(async_in), .sync_out(sync_out));

always #5 clk = ~clk; // Clock toggles every 5 time units

initial begin
    async_in = 1;
    #20;
    $display("Synchronized output: %b", sync_out);
    $finish;
end

// Your code here
endmodule

Hint

Use a testbench to toggle the clock and input, then display the synchronized output.

Practice

1. What is the main purpose of a synchronizer in Verilog designs?

easy

A. To generate reset signals for flip-flops

B. To reduce metastability by allowing signals to settle before use

C. To convert analog signals to digital

D. To increase clock frequency for faster operation

Solution

1. Step 1: Understand metastability

   Metastability occurs when signals change close to clock edges, causing uncertain outputs.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to give signals time to stabilize and avoid metastability effects.

3. Final Answer:

   To reduce metastability by allowing signals to settle before use -> Option B

4. Quick Check:

   Synchronizer purpose = reduce metastability [OK]

Hint: Synchronizers help signals settle before use to avoid errors [OK]

Common Mistakes:

• Thinking synchronizers speed up clocks
• Confusing synchronizers with reset generators
• Assuming synchronizers convert signal types

2. Which Verilog code snippet correctly implements a 2-stage synchronizer for an asynchronous input async_in?

easy

A. reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end

B. reg sync1; always @(negedge clk) sync1 <= async_in;

C. wire sync1 = async_in; wire sync2 = sync1;

D. reg sync1, sync2; always @(posedge clk) begin sync2 <= async_in; sync1 <= sync2; end

Solution

1. Step 1: Identify correct synchronizer structure

   A 2-stage synchronizer uses two flip-flops in series clocked by the same clock.

2. Step 2: Check code correctness

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end correctly assigns sync1 first, then sync2 on the clock's rising edge, matching the synchronizer design.

3. Final Answer:

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end -> Option A

4. Quick Check:

   Two flip-flops in series = reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end [OK]

Hint: Synchronizer uses two flip-flops clocked on posedge [OK]

Common Mistakes:

• Using negedge clock instead of posedge
• Assigning signals in wrong order
• Using wires instead of regs for flip-flops

3. Given the following Verilog code, what is the output value of sync_out after two clock cycles if async_in changes from 0 to 1 just before the first clock edge?

reg sync1, sync2;
always @(posedge clk) begin
  sync1 <= async_in;
  sync2 <= sync1;
end
assign sync_out = sync2;

medium

A. sync_out becomes 1 after two clock cycles

B. sync_out becomes 1 immediately at first clock edge

C. sync_out remains 0 indefinitely

D. sync_out toggles between 0 and 1 every clock

Solution

1. Step 1: Trace signal through synchronizer stages

   At first clock edge, sync1 captures async_in=1, but sync2 still holds old sync1 value (0).

2. Step 2: After second clock edge

   At second clock edge, sync2 captures sync1=1, so sync_out becomes 1.

3. Final Answer:

   sync_out becomes 1 after two clock cycles -> Option A

4. Quick Check:

   Two flip-flop delay = output after two clocks [OK]

Hint: Synchronizer output updates after two clock cycles [OK]

Common Mistakes:

• Assuming output changes immediately
• Ignoring flip-flop delay stages
• Confusing sync1 and sync2 roles

4. Identify the error in this synchronizer code snippet:

reg sync1, sync2;
always @(posedge clk) begin
  sync2 <= async_in;
  sync1 <= sync2;
end

medium

A. Clock edge should be negedge instead of posedge

B. Missing asynchronous reset signal

C. Using blocking assignments instead of non-blocking

D. The flip-flop assignments are reversed; sync1 should capture async_in first

Solution

1. Step 1: Analyze assignment order

   The first flip-flop should capture async_in, then the second captures the first flip-flop's output.

2. Step 2: Identify reversed assignments

   Here, sync2 captures async_in first, which is incorrect; sync1 should capture async_in first.

3. Final Answer:

   The flip-flop assignments are reversed; sync1 should capture async_in first -> Option D

4. Quick Check:

   Correct order: sync1 <= async_in; sync2 <= sync1 [OK]

Hint: First flip-flop captures async input, second captures first flip-flop [OK]

Common Mistakes:

• Swapping flip-flop assignment order
• Forgetting non-blocking assignments
• Assuming reset is mandatory for synchronizers

5. You need to design a synchronizer for a signal coming from a different clock domain that toggles very fast. Which approach best reduces metastability risk and ensures stable output?

hard

A. Use combinational logic to directly sample the asynchronous signal

B. Use a single flip-flop synchronizer with asynchronous reset

C. Use a 3-stage synchronizer with flip-flops clocked by the receiving clock

D. Use a 2-stage synchronizer clocked by the source clock

Solution

1. Step 1: Understand metastability risk with fast toggling signals

   Fast toggling signals crossing clock domains increase metastability risk; more synchronization stages help reduce it.

2. Step 2: Choose proper synchronizer design

   A 3-stage synchronizer clocked by the receiving clock provides more settling time and reduces metastability better than fewer stages or wrong clock domains.

3. Final Answer:

   Use a 3-stage synchronizer with flip-flops clocked by the receiving clock -> Option C

4. Quick Check:

   More stages + receiving clock = better metastability reduction [OK]

Hint: More flip-flop stages reduce metastability risk [OK]

Common Mistakes:

• Using source clock instead of receiving clock
• Using too few synchronizer stages
• Sampling asynchronously with combinational logic