Metastability and synchronizer design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a D flip-flop with asynchronous reset.

Verilog

always @(posedge clk or posedge rst) begin
  if ([1]) q <= 0;
  else q <= d;
end

Drag options to blanks, or click blank then click option'

Arst

Bclk

Cd

Dq

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' instead of 'rst' in the if condition.

Checking data input 'd' instead of reset.

The asynchronous reset signal is checked first to clear the output.

2fill in blank

medium

Complete the code to instantiate a 2-stage synchronizer for an asynchronous input signal.

Verilog

reg sync_0, sync_1;
always @(posedge clk) begin
  sync_0 <= async_in;
  [1] <= sync_0;
end

Drag options to blanks, or click blank then click option'

Aasync_in

Bclk

Csync_0

Dsync_1

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning 'sync_0' to itself.

Using 'async_in' directly in the second register.

The second stage register 'sync_1' captures the output of the first stage 'sync_0'.

3fill in blank

hard

Fix the error in the synchronizer code to avoid combinational loop.

Verilog

always @(posedge clk) begin
  sync_0 <= async_in;
  sync_1 <= [1];
end

Drag options to blanks, or click blank then click option'

Async_0

Bclk

Casync_in

Dsync_1

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning 'sync_1' to itself causing a loop.

Using 'async_in' directly in the second register.

The second register must capture the first register's value to avoid combinational loops.

4fill in blank

hard

Fill both blanks to complete the metastability flag logic in a synchronizer.

Verilog

reg meta_flag;
always @(posedge clk) begin
  meta_flag <= ([1] != [2]);
end

Drag options to blanks, or click blank then click option'

Async_1

Bsync_0

Casync_in

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Comparing to the clock signal.

Using the asynchronous input directly.

The flag detects when the first and second stage differ, indicating possible metastability.

5fill in blank

hard

Fill all three blanks to complete the code for a 3-stage synchronizer with metastability detection.

Verilog

reg sync_0, sync_1, sync_2;
reg meta_flag;
always @(posedge clk) begin
  sync_0 <= [1];
  sync_1 <= [2];
  sync_2 <= [3];
  meta_flag <= (sync_0 != sync_1) || (sync_1 != sync_2);
end

Drag options to blanks, or click blank then click option'

Aasync_in

Bsync_0

Csync_1

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning the clock signal to a synchronizer stage.

Skipping stages or assigning wrong signals.

The first stage captures the async input, the second captures the first, and the third captures the second to reduce metastability risk.

Practice

1. What is the main purpose of a synchronizer in Verilog designs?

easy

A. To generate reset signals for flip-flops

B. To reduce metastability by allowing signals to settle before use

C. To convert analog signals to digital

D. To increase clock frequency for faster operation

Solution

1. Step 1: Understand metastability

   Metastability occurs when signals change close to clock edges, causing uncertain outputs.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to give signals time to stabilize and avoid metastability effects.

3. Final Answer:

   To reduce metastability by allowing signals to settle before use -> Option B

4. Quick Check:

   Synchronizer purpose = reduce metastability [OK]

Hint: Synchronizers help signals settle before use to avoid errors [OK]

Common Mistakes:

• Thinking synchronizers speed up clocks
• Confusing synchronizers with reset generators
• Assuming synchronizers convert signal types

2. Which Verilog code snippet correctly implements a 2-stage synchronizer for an asynchronous input async_in?

easy

A. reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end

B. reg sync1; always @(negedge clk) sync1 <= async_in;

C. wire sync1 = async_in; wire sync2 = sync1;

D. reg sync1, sync2; always @(posedge clk) begin sync2 <= async_in; sync1 <= sync2; end

Solution

1. Step 1: Identify correct synchronizer structure

   A 2-stage synchronizer uses two flip-flops in series clocked by the same clock.

2. Step 2: Check code correctness

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end correctly assigns sync1 first, then sync2 on the clock's rising edge, matching the synchronizer design.

3. Final Answer:

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end -> Option A

4. Quick Check:

   Two flip-flops in series = reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end [OK]

Hint: Synchronizer uses two flip-flops clocked on posedge [OK]

Common Mistakes:

• Using negedge clock instead of posedge
• Assigning signals in wrong order
• Using wires instead of regs for flip-flops

3. Given the following Verilog code, what is the output value of sync_out after two clock cycles if async_in changes from 0 to 1 just before the first clock edge?

reg sync1, sync2;
always @(posedge clk) begin
  sync1 <= async_in;
  sync2 <= sync1;
end
assign sync_out = sync2;

medium

A. sync_out becomes 1 after two clock cycles

B. sync_out becomes 1 immediately at first clock edge

C. sync_out remains 0 indefinitely

D. sync_out toggles between 0 and 1 every clock

Solution

1. Step 1: Trace signal through synchronizer stages

   At first clock edge, sync1 captures async_in=1, but sync2 still holds old sync1 value (0).

2. Step 2: After second clock edge

   At second clock edge, sync2 captures sync1=1, so sync_out becomes 1.

3. Final Answer:

   sync_out becomes 1 after two clock cycles -> Option A

4. Quick Check:

   Two flip-flop delay = output after two clocks [OK]

Hint: Synchronizer output updates after two clock cycles [OK]

Common Mistakes:

• Assuming output changes immediately
• Ignoring flip-flop delay stages
• Confusing sync1 and sync2 roles

4. Identify the error in this synchronizer code snippet:

reg sync1, sync2;
always @(posedge clk) begin
  sync2 <= async_in;
  sync1 <= sync2;
end

medium

A. Clock edge should be negedge instead of posedge

B. Missing asynchronous reset signal

C. Using blocking assignments instead of non-blocking

D. The flip-flop assignments are reversed; sync1 should capture async_in first

Solution

1. Step 1: Analyze assignment order

   The first flip-flop should capture async_in, then the second captures the first flip-flop's output.

2. Step 2: Identify reversed assignments

   Here, sync2 captures async_in first, which is incorrect; sync1 should capture async_in first.

3. Final Answer:

   The flip-flop assignments are reversed; sync1 should capture async_in first -> Option D

4. Quick Check:

   Correct order: sync1 <= async_in; sync2 <= sync1 [OK]

Hint: First flip-flop captures async input, second captures first flip-flop [OK]

Common Mistakes:

• Swapping flip-flop assignment order
• Forgetting non-blocking assignments
• Assuming reset is mandatory for synchronizers

5. You need to design a synchronizer for a signal coming from a different clock domain that toggles very fast. Which approach best reduces metastability risk and ensures stable output?

hard

A. Use combinational logic to directly sample the asynchronous signal

B. Use a single flip-flop synchronizer with asynchronous reset

C. Use a 3-stage synchronizer with flip-flops clocked by the receiving clock

D. Use a 2-stage synchronizer clocked by the source clock

Solution

1. Step 1: Understand metastability risk with fast toggling signals

   Fast toggling signals crossing clock domains increase metastability risk; more synchronization stages help reduce it.

2. Step 2: Choose proper synchronizer design

   A 3-stage synchronizer clocked by the receiving clock provides more settling time and reduces metastability better than fewer stages or wrong clock domains.

3. Final Answer:

   Use a 3-stage synchronizer with flip-flops clocked by the receiving clock -> Option C

4. Quick Check:

   More stages + receiving clock = better metastability reduction [OK]

Hint: More flip-flop stages reduce metastability risk [OK]

Common Mistakes:

• Using source clock instead of receiving clock
• Using too few synchronizer stages
• Sampling asynchronously with combinational logic