Debouncer circuit design in Verilog - Step-by-Step Execution

Concept Flow - Debouncer circuit design

Input: Noisy Button Signal

↓

Sample Input at Clock Rate

↓

Check if Input Stable

↓

Increment Counter

↓

Counter Reaches Limit?

↓

Update Output

↓

Clean, Debounced Output

The debouncer samples the noisy input repeatedly. If the input stays the same for enough cycles, it updates the output. Otherwise, it resets the count and waits.

Execution Sample

Verilog

module debouncer(
  input clk,
  input noisy_in,
  output reg clean_out
);
  // debounce logic
endmodule

This module cleans a noisy button signal by waiting for it to be stable before changing the output.

Execution Table

Step	Clock Cycle	Noisy Input	Counter Value	Condition (Input Stable?)	Action	Output (clean_out)
1	1	1	1	Yes	Increment Counter	0
2	2	1	2	Yes	Increment Counter	0
3	3	0	0	No (input changed)	Reset Counter	0
4	4	0	1	Yes	Increment Counter	0
5	5	0	2	Yes	Increment Counter	0
6	6	0	3	Yes	Counter reached limit, update output	0
7	7	0	3	Yes	Output stable	0
8	8	1	0	No (input changed)	Reset Counter	0
9	9	1	1	Yes	Increment Counter	0
10	10	1	2	Yes	Increment Counter	0
11	11	1	3	Yes	Counter reached limit, update output	1
12	12	1	3	Yes	Output stable	1

💡 Simulation ends after output stabilizes following stable input periods.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
noisy_in	0	1	1	0	0	0	0	0	1	1	1	1	1
counter	0	1	2	0	1	2	3	3	0	1	2	3	3
clean_out	0	0	0	0	0	0	0	0	0	0	0	1	1

Key Moments - 3 Insights

Why does the counter reset when the input changes?

Because the input is not stable, the debouncer resets the counter to wait for a stable signal period before updating the output, as shown in steps 3 and 8 in the execution_table.

When does the output actually change?

The output changes only after the counter reaches the limit, meaning the input has been stable for enough cycles. This happens at step 11 in the execution_table.

Why does the output stay the same even if the input changes briefly?

Because the output updates only after stable input periods, brief changes reset the counter but do not immediately affect the output, ensuring a clean signal as seen between steps 7 and 8.

Visual Quiz - 3 Questions

Look at the execution_table at step 3. What happens to the counter and why?

A Counter increments because input is stable

B Counter resets because input changed

C Output changes immediately

D Nothing happens

💡 Hint

Check the 'Condition (Input Stable?)' and 'Action' columns at step 3 in execution_table.

At which clock cycle does the output first change to 1?

A 6

B 7

C 11

D 12

💡 Hint

Look at the 'Output (clean_out)' column in execution_table and find when it changes from 0 to 1.

If the input stayed stable at 1 from the start, how would the counter behave?

A It would increment each cycle until limit

B It would stay at zero

C It would reset every cycle

D It would randomly change

💡 Hint

Refer to variable_tracker for 'counter' increments when input is stable.

Concept Snapshot

Debouncer circuit waits for input to be stable for several clock cycles.
It samples input each clock.
If input changes, counter resets.
If input stable, counter increments.
When counter hits limit, output updates.
This removes noise from button presses.

Full Transcript

A debouncer circuit cleans a noisy button signal by sampling it repeatedly at each clock cycle. If the input stays the same for enough cycles, the circuit updates the output to that stable value. If the input changes, the counter resets to zero and waits again. This process ensures the output only changes when the input is stable, removing noise from quick button presses or bounces. The execution table shows each clock cycle's input, counter value, condition check, action taken, and output. The variable tracker follows how the input, counter, and output change step by step. Key moments clarify why the counter resets on input change and when the output updates. The visual quiz tests understanding of these steps. This design is common in hardware to get clean signals from mechanical switches.

Practice

1.

What is the main purpose of a debouncer circuit in Verilog?

easy

A. To convert analog signals to digital

B. To increase the clock speed of the circuit

C. To generate random signals for testing

D. To clean noisy button signals and produce a stable output

Solution

1. Step 1: Understand the problem of noisy signals

   Mechanical buttons often produce multiple quick on/off signals (noise) when pressed.

2. Step 2: Role of debouncer

   A debouncer waits for the input to be stable for some time before changing the output, thus cleaning the noise.

3. Final Answer:

   To clean noisy button signals and produce a stable output -> Option D

4. Quick Check:

   Debouncer = Clean noisy signals [OK]

Hint: Debouncer = stable output from noisy input [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog to digital converter
• Assuming debouncer generates signals

2.

Which of the following is the correct way to declare a 16-bit counter register in Verilog?

?

easy

A. wire [16:0] counter;

B. reg [15:0] counter;

C. reg counter[15:0];

D. integer counter[16];

Solution

1. Step 1: Understand Verilog register declaration

   Registers use 'reg' keyword and bit width is declared as [MSB:LSB].

2. Step 2: Check each option

   reg [15:0] counter; correctly declares a 16-bit register from bit 15 down to 0.

3. Final Answer:

   reg [15:0] counter; -> Option B

4. Quick Check:

   16-bit reg = reg [15:0] name; [OK]

Hint: Use reg [15:0] for 16-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Declaring arrays instead of bit vectors

3.

Given this Verilog snippet for a debouncer counter:

always @(posedge clk) begin
  if (button == last_button) begin
    if (counter < 3) counter <= counter + 1;
  end else counter <= 0;
  last_button <= button;
end

What is the value of counter after 5 clock cycles if button stays stable at 1?

medium

A. 5

B. 0

C. 3

D. 1

Solution

1. Step 1: Analyze counter increment condition

   Counter increments only if button equals last_button and counter is less than 3.

2. Step 2: Trace counter over 5 cycles

   Initially counter=0. It increments each cycle until it reaches 3, then stops incrementing.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Counter maxes at 3 despite 5 cycles [OK]

Hint: Counter stops incrementing at max value 3 [OK]

Common Mistakes:

• Assuming counter increments beyond 3
• Ignoring last_button update
• Resetting counter incorrectly

4.

Identify the error in this debouncer code snippet:

reg [3:0] counter;
reg last_button;
always @(posedge clk) begin
  if (button == last_button) begin
    counter = counter + 1;
  end else begin
    counter = 0;
  end
  last_button = button;
end

medium

A. Using blocking assignments (=) inside always block for sequential logic

B. Missing sensitivity list for asynchronous reset

C. Counter width too small for debounce time

D. No initial value for last_button

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic should use non-blocking assignments (<=) to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) inside a clocked always block, which is incorrect.

3. Final Answer:

   Using blocking assignments (=) inside always block for sequential logic -> Option A

4. Quick Check:

   Use <= for sequential logic assignments [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Ignoring sensitivity list importance
• Assuming initial values fix assignment errors

5.

You want to design a debouncer that waits for 10ms of stable input before changing output. The clock frequency is 1MHz. How many bits should the counter have at minimum?

hard

A. 14 bits

B. 10 bits

C. 20 bits

D. 8 bits

Solution

1. Step 1: Calculate required count for 10ms at 1MHz clock

   10ms = 0.01 seconds. Clock period = 1us (1/1MHz). Number of counts = 0.01 / 0.000001 = 10,000 counts.

2. Step 2: Find minimum bits to count 10,000

   2^13 = 8192 (too small), 2^14 = 16384 (enough). So minimum 14 bits needed.

3. Final Answer:

   14 bits -> Option A

4. Quick Check:

   10,000 < 2^14 = 16384 [OK]

Hint: Count = time * clock freq; bits = ceil(log2(count)) [OK]

Common Mistakes:

• Using clock frequency as count directly
• Choosing too few bits to cover count
• Confusing ms and us units