Debouncer circuit design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the input signal for the debouncer module.

Verilog

module debouncer(
    input wire [1],
    output reg clean_out
);

Drag options to blanks, or click blank then click option'

Aclk

Bnoisy_in

Creset

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' as input signal to debounce instead of the noisy input.

Confusing reset signal with input signal.

The input signal to be debounced is usually called noisy_in.

2fill in blank

medium

Complete the code to declare a 16-bit register for the counter.

Verilog

reg [[1]:0] counter;

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A16

B31

C15

D7

Attempts:

3 left

💡 Hint

Common Mistakes

Using 16 instead of 15 as the upper index.

Confusing bit width with index range.

A 16-bit register is declared as [15:0] because indexing starts at 0.

3fill in blank

hard

Fix the error in the always block sensitivity list to include the clock signal.

Verilog

always @([1]) begin
    if (reset) begin
        counter <= 0;
    end else if (noisy_in == clean_out) begin
        counter <= 0;
    end else begin
        counter <= counter + 1;
    end
end

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Anegedge reset

Bnoisy_in

Cclean_out

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using asynchronous signals in sensitivity list causing glitches.

Forgetting to include clock in sensitivity list.

The always block should be triggered on the positive edge of the clock for synchronous logic.

4fill in blank

hard

Fill both blanks to complete the condition that resets the counter when stable and sets the output.

Verilog

if (counter == [1]) begin
    clean_out <= [2];
end

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AMAX_COUNT

Bnoisy_in

C1'b1

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using a fixed number instead of a parameter like MAX_COUNT.

Assigning output to a constant instead of the input signal.

The counter resets when it reaches MAX_COUNT, and the output is set to the stable noisy_in value.

5fill in blank

hard

Fill all three blanks to complete the parameter declaration, the counter increment, and the output assignment.

Verilog

parameter [1] = 16'hFFFF;

always @(posedge clk) begin
    if (reset) begin
        counter <= 0;
        clean_out <= 0;
    end else if (noisy_in == clean_out) begin
        counter <= 0;
    end else if (counter < [2]) begin
        counter <= counter + [3];
    end else begin
        clean_out <= noisy_in;
    end
end

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AMAX_COUNT

C1

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using different names for the parameter in different places.

Incrementing counter by 0 or wrong value.

The parameter MAX_COUNT defines the debounce time. The counter increments by 1 until it reaches MAX_COUNT.

Practice

1.

What is the main purpose of a debouncer circuit in Verilog?

easy

A. To convert analog signals to digital

B. To increase the clock speed of the circuit

C. To generate random signals for testing

D. To clean noisy button signals and produce a stable output

Solution

1. Step 1: Understand the problem of noisy signals

   Mechanical buttons often produce multiple quick on/off signals (noise) when pressed.

2. Step 2: Role of debouncer

   A debouncer waits for the input to be stable for some time before changing the output, thus cleaning the noise.

3. Final Answer:

   To clean noisy button signals and produce a stable output -> Option D

4. Quick Check:

   Debouncer = Clean noisy signals [OK]

Hint: Debouncer = stable output from noisy input [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog to digital converter
• Assuming debouncer generates signals

2.

Which of the following is the correct way to declare a 16-bit counter register in Verilog?

?

easy

A. wire [16:0] counter;

B. reg [15:0] counter;

C. reg counter[15:0];

D. integer counter[16];

Solution

1. Step 1: Understand Verilog register declaration

   Registers use 'reg' keyword and bit width is declared as [MSB:LSB].

2. Step 2: Check each option

   reg [15:0] counter; correctly declares a 16-bit register from bit 15 down to 0.

3. Final Answer:

   reg [15:0] counter; -> Option B

4. Quick Check:

   16-bit reg = reg [15:0] name; [OK]

Hint: Use reg [15:0] for 16-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Declaring arrays instead of bit vectors

3.

Given this Verilog snippet for a debouncer counter:

always @(posedge clk) begin
  if (button == last_button) begin
    if (counter < 3) counter <= counter + 1;
  end else counter <= 0;
  last_button <= button;
end

What is the value of counter after 5 clock cycles if button stays stable at 1?

medium

A. 5

B. 0

C. 3

D. 1

Solution

1. Step 1: Analyze counter increment condition

   Counter increments only if button equals last_button and counter is less than 3.

2. Step 2: Trace counter over 5 cycles

   Initially counter=0. It increments each cycle until it reaches 3, then stops incrementing.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Counter maxes at 3 despite 5 cycles [OK]

Hint: Counter stops incrementing at max value 3 [OK]

Common Mistakes:

• Assuming counter increments beyond 3
• Ignoring last_button update
• Resetting counter incorrectly

4.

Identify the error in this debouncer code snippet:

reg [3:0] counter;
reg last_button;
always @(posedge clk) begin
  if (button == last_button) begin
    counter = counter + 1;
  end else begin
    counter = 0;
  end
  last_button = button;
end

medium

A. Using blocking assignments (=) inside always block for sequential logic

B. Missing sensitivity list for asynchronous reset

C. Counter width too small for debounce time

D. No initial value for last_button

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic should use non-blocking assignments (<=) to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) inside a clocked always block, which is incorrect.

3. Final Answer:

   Using blocking assignments (=) inside always block for sequential logic -> Option A

4. Quick Check:

   Use <= for sequential logic assignments [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Ignoring sensitivity list importance
• Assuming initial values fix assignment errors

5.

You want to design a debouncer that waits for 10ms of stable input before changing output. The clock frequency is 1MHz. How many bits should the counter have at minimum?

hard

A. 14 bits

B. 10 bits

C. 20 bits

D. 8 bits

Solution

1. Step 1: Calculate required count for 10ms at 1MHz clock

   10ms = 0.01 seconds. Clock period = 1us (1/1MHz). Number of counts = 0.01 / 0.000001 = 10,000 counts.

2. Step 2: Find minimum bits to count 10,000

   2^13 = 8192 (too small), 2^14 = 16384 (enough). So minimum 14 bits needed.

3. Final Answer:

   14 bits -> Option A

4. Quick Check:

   10,000 < 2^14 = 16384 [OK]

Hint: Count = time * clock freq; bits = ceil(log2(count)) [OK]

Common Mistakes:

• Using clock frequency as count directly
• Choosing too few bits to cover count
• Confusing ms and us units