Debouncer circuit design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this debouncer module simulation?

Consider this Verilog debouncer module and testbench snippet. What will be the stable output signal debounced_out after the input noisy_in bounces and settles?

Verilog

module debouncer(
  input clk,
  input noisy_in,
  output reg debounced_out
);
  reg [3:0] shift_reg = 4'b0000;
  always @(posedge clk) begin
    shift_reg <= {shift_reg[2:0], noisy_in};
    if (shift_reg == 4'b1111)
      debounced_out <= 1'b1;
    else if (shift_reg == 4'b0000)
      debounced_out <= 1'b0;
  end
endmodule

// Testbench snippet
// clk toggles every 5 time units
// noisy_in changes: 0->1->0->1->1->1->1
// after 7 clock cycles

A debounced_out remains undefined

B debounced_out = 1

C debounced_out toggles rapidly

D debounced_out = 0

💡 Hint

Think about how the shift register collects consecutive input samples and when the output changes.

The debouncer waits for 4 consecutive '1's to set debounced_out to 1. After the noisy input settles to 1 for 4 cycles, the output becomes 1.

🧠 Conceptual

intermediate

What is the main purpose of a debouncer circuit in digital design?

Choose the best description of what a debouncer circuit does.

A It generates clock signals for synchronous circuits.

B It amplifies weak input signals to stronger levels.

C It converts analog signals to digital signals.

D It filters out rapid on/off transitions caused by mechanical switch bouncing.

💡 Hint

Think about what happens when you press a mechanical button and the signal is noisy.

Mechanical switches often produce multiple rapid transitions (bounces) when toggled. A debouncer circuit removes these unwanted transitions to produce a clean, stable signal.

🔧 Debug

advanced

Why does this Verilog debouncer code fail to debounce correctly?

Examine the following Verilog code snippet for a debouncer. It does not debounce the input as expected. What is the main issue?

Verilog

module debouncer(
  input clk,
  input noisy_in,
  output reg debounced_out
);
  reg [3:0] shift_reg;
  always @(posedge clk) begin
    shift_reg <= {shift_reg[2:0], noisy_in};
    if (shift_reg == 4'b1111)
      debounced_out <= 1'b1;
    else
      debounced_out <= 1'b0;
  end
endmodule

A debounced_out resets to 0 immediately when shift_reg is not 1111, causing output to flicker

B shift_reg is not initialized, causing unpredictable behavior

C The clock signal is missing from the sensitivity list

D The module lacks asynchronous reset logic

💡 Hint

Consider what happens when the input is not stable and how the output changes.

The code sets debounced_out to 0 whenever the shift register is not all ones, causing the output to flicker instead of holding the stable state.

📝 Syntax

advanced

Which option correctly declares a 16-bit counter register in Verilog?

Choose the correct syntax to declare a 16-bit register named counter in Verilog.

A reg [15:0] counter;

B reg counter : 16;

C reg counter[15:0];

D reg [0:15] counter;

💡 Hint

Remember that Verilog uses [msb:lsb] notation for bit ranges.

The correct syntax for a 16-bit register is reg [15:0] counter;. Option A declares an array of 16 1-bit registers, not a 16-bit register.

🚀 Application

expert

How many clock cycles minimum are needed for this debouncer to confirm a stable input?

Given a debouncer that uses an 8-bit shift register sampling the input every clock cycle, how many consecutive identical input samples are required before the output changes state?

A 1 clock cycle

B 7 clock cycles

C 8 clock cycles

D 16 clock cycles

💡 Hint

Think about how many bits in the shift register must be the same to confirm stability.

The debouncer waits until all 8 bits in the shift register match the input value, so it requires 8 consecutive identical samples.

Practice

1.

What is the main purpose of a debouncer circuit in Verilog?

easy

A. To convert analog signals to digital

B. To increase the clock speed of the circuit

C. To generate random signals for testing

D. To clean noisy button signals and produce a stable output

Solution

1. Step 1: Understand the problem of noisy signals

   Mechanical buttons often produce multiple quick on/off signals (noise) when pressed.

2. Step 2: Role of debouncer

   A debouncer waits for the input to be stable for some time before changing the output, thus cleaning the noise.

3. Final Answer:

   To clean noisy button signals and produce a stable output -> Option D

4. Quick Check:

   Debouncer = Clean noisy signals [OK]

Hint: Debouncer = stable output from noisy input [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog to digital converter
• Assuming debouncer generates signals

2.

Which of the following is the correct way to declare a 16-bit counter register in Verilog?

?

easy

A. wire [16:0] counter;

B. reg [15:0] counter;

C. reg counter[15:0];

D. integer counter[16];

Solution

1. Step 1: Understand Verilog register declaration

   Registers use 'reg' keyword and bit width is declared as [MSB:LSB].

2. Step 2: Check each option

   reg [15:0] counter; correctly declares a 16-bit register from bit 15 down to 0.

3. Final Answer:

   reg [15:0] counter; -> Option B

4. Quick Check:

   16-bit reg = reg [15:0] name; [OK]

Hint: Use reg [15:0] for 16-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Declaring arrays instead of bit vectors

3.

Given this Verilog snippet for a debouncer counter:

always @(posedge clk) begin
  if (button == last_button) begin
    if (counter < 3) counter <= counter + 1;
  end else counter <= 0;
  last_button <= button;
end

What is the value of counter after 5 clock cycles if button stays stable at 1?

medium

A. 5

B. 0

C. 3

D. 1

Solution

1. Step 1: Analyze counter increment condition

   Counter increments only if button equals last_button and counter is less than 3.

2. Step 2: Trace counter over 5 cycles

   Initially counter=0. It increments each cycle until it reaches 3, then stops incrementing.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Counter maxes at 3 despite 5 cycles [OK]

Hint: Counter stops incrementing at max value 3 [OK]

Common Mistakes:

• Assuming counter increments beyond 3
• Ignoring last_button update
• Resetting counter incorrectly

4.

Identify the error in this debouncer code snippet:

reg [3:0] counter;
reg last_button;
always @(posedge clk) begin
  if (button == last_button) begin
    counter = counter + 1;
  end else begin
    counter = 0;
  end
  last_button = button;
end

medium

A. Using blocking assignments (=) inside always block for sequential logic

B. Missing sensitivity list for asynchronous reset

C. Counter width too small for debounce time

D. No initial value for last_button

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic should use non-blocking assignments (<=) to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) inside a clocked always block, which is incorrect.

3. Final Answer:

   Using blocking assignments (=) inside always block for sequential logic -> Option A

4. Quick Check:

   Use <= for sequential logic assignments [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Ignoring sensitivity list importance
• Assuming initial values fix assignment errors

5.

You want to design a debouncer that waits for 10ms of stable input before changing output. The clock frequency is 1MHz. How many bits should the counter have at minimum?

hard

A. 14 bits

B. 10 bits

C. 20 bits

D. 8 bits

Solution

1. Step 1: Calculate required count for 10ms at 1MHz clock

   10ms = 0.01 seconds. Clock period = 1us (1/1MHz). Number of counts = 0.01 / 0.000001 = 10,000 counts.

2. Step 2: Find minimum bits to count 10,000

   2^13 = 8192 (too small), 2^14 = 16384 (enough). So minimum 14 bits needed.

3. Final Answer:

   14 bits -> Option A

4. Quick Check:

   10,000 < 2^14 = 16384 [OK]

Hint: Count = time * clock freq; bits = ceil(log2(count)) [OK]

Common Mistakes:

• Using clock frequency as count directly
• Choosing too few bits to cover count
• Confusing ms and us units