Debouncer circuit design in Verilog - Mini Project: Build & Apply

Debouncer Circuit Design in Verilog

📖 Scenario: In digital electronics, mechanical switches often produce noisy signals when pressed or released. This noise causes multiple unwanted transitions called 'bouncing'. To get a clean, stable signal, we use a debouncer circuit.Imagine you want to build a simple debouncer for a push-button switch in your digital project.

🎯 Goal: You will create a Verilog module that takes a noisy button input and outputs a clean, stable signal after debouncing.

📋 What You'll Learn

Create a register to hold the button input state

Add a counter to measure stable input time

Implement logic to update output only after input is stable for a set time

Output the debounced button signal

💡 Why This Matters

🌍 Real World

Debouncer circuits are essential in hardware projects to ensure reliable button presses without false triggers caused by mechanical noise.

💼 Career

Understanding debouncer design is important for hardware engineers and FPGA developers working on embedded systems and digital interfaces.

1

Create the module and input/output ports

Write a Verilog module named debouncer with inputs clk and noisy_in, and output clean_out. Declare clean_out as a reg type.

Verilog

module debouncer(
    input clk,
    input noisy_in,
    output reg clean_out
);

// Your code here

endmodule

Hint

Start by defining the module and its ports exactly as described.

2

Add registers for input sampling and a counter

Inside the debouncer module, declare a 16-bit register called counter initialized to 0, and a 1-bit register called button_sync initialized to 0.

Verilog

module debouncer(
    input clk,
    input noisy_in,
    output reg clean_out
);

reg [15:0] counter = 0;
reg button_sync = 0;
// Your code here

endmodule

Hint

Use reg [15:0] counter = 0; and reg button_sync = 0; inside the module.

3

Implement the debouncing logic in an always block

Add an always @(posedge clk) block inside the module. Inside it, assign button_sync = noisy_in. Then, if button_sync equals noisy_in, increment counter until it reaches 50000. If they differ, reset counter to 0. When counter reaches 50000, set clean_out = button_sync.

Verilog

module debouncer(
    input clk,
    input noisy_in,
    output reg clean_out
);

reg [15:0] counter = 0;
reg button_sync = 0;

always @(posedge clk) begin
    // Your code here
end

endmodule

Hint

Use a clocked always block to sample input and count stable cycles before updating output.

4

Test the debouncer output with a print statement

Add a testbench module named testbench that instantiates debouncer. Simulate a noisy input sequence and use $display to print clean_out after each clock cycle.

Verilog

module debouncer(
    input clk,
    input noisy_in,
    output reg clean_out
);

reg [15:0] counter = 0;
reg button_sync = 0;

always @(posedge clk) begin
    button_sync <= noisy_in;
    if (button_sync == noisy_in) begin
        if (counter < 16'd50000) begin
            counter <= counter + 1;
        end else begin
            clean_out <= button_sync;
        end
    end else begin
        counter <= 0;
    end
end

endmodule

module testbench;
    reg clk = 0;
    reg noisy_in = 0;
    wire clean_out;

    debouncer uut(.clk(clk), .noisy_in(noisy_in), .clean_out(clean_out));

    always #1 clk = ~clk;

    initial begin
        // Your code here
    end
endmodule

Hint

Create a testbench to simulate the debouncer and print the stable output.

Practice

1.

What is the main purpose of a debouncer circuit in Verilog?

easy

A. To convert analog signals to digital

B. To increase the clock speed of the circuit

C. To generate random signals for testing

D. To clean noisy button signals and produce a stable output

Solution

1. Step 1: Understand the problem of noisy signals

   Mechanical buttons often produce multiple quick on/off signals (noise) when pressed.

2. Step 2: Role of debouncer

   A debouncer waits for the input to be stable for some time before changing the output, thus cleaning the noise.

3. Final Answer:

   To clean noisy button signals and produce a stable output -> Option D

4. Quick Check:

   Debouncer = Clean noisy signals [OK]

Hint: Debouncer = stable output from noisy input [OK]

Common Mistakes:

• Thinking debouncer speeds up the clock
• Confusing debouncer with analog to digital converter
• Assuming debouncer generates signals

2.

Which of the following is the correct way to declare a 16-bit counter register in Verilog?

?

easy

A. wire [16:0] counter;

B. reg [15:0] counter;

C. reg counter[15:0];

D. integer counter[16];

Solution

1. Step 1: Understand Verilog register declaration

   Registers use 'reg' keyword and bit width is declared as [MSB:LSB].

2. Step 2: Check each option

   reg [15:0] counter; correctly declares a 16-bit register from bit 15 down to 0.

3. Final Answer:

   reg [15:0] counter; -> Option B

4. Quick Check:

   16-bit reg = reg [15:0] name; [OK]

Hint: Use reg [15:0] for 16-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Declaring arrays instead of bit vectors

3.

Given this Verilog snippet for a debouncer counter:

always @(posedge clk) begin
  if (button == last_button) begin
    if (counter < 3) counter <= counter + 1;
  end else counter <= 0;
  last_button <= button;
end

What is the value of counter after 5 clock cycles if button stays stable at 1?

medium

A. 5

B. 0

C. 3

D. 1

Solution

1. Step 1: Analyze counter increment condition

   Counter increments only if button equals last_button and counter is less than 3.

2. Step 2: Trace counter over 5 cycles

   Initially counter=0. It increments each cycle until it reaches 3, then stops incrementing.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Counter maxes at 3 despite 5 cycles [OK]

Hint: Counter stops incrementing at max value 3 [OK]

Common Mistakes:

• Assuming counter increments beyond 3
• Ignoring last_button update
• Resetting counter incorrectly

4.

Identify the error in this debouncer code snippet:

reg [3:0] counter;
reg last_button;
always @(posedge clk) begin
  if (button == last_button) begin
    counter = counter + 1;
  end else begin
    counter = 0;
  end
  last_button = button;
end

medium

A. Using blocking assignments (=) inside always block for sequential logic

B. Missing sensitivity list for asynchronous reset

C. Counter width too small for debounce time

D. No initial value for last_button

Solution

1. Step 1: Check assignment types in sequential always block

   Sequential logic should use non-blocking assignments (<=) to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) inside a clocked always block, which is incorrect.

3. Final Answer:

   Using blocking assignments (=) inside always block for sequential logic -> Option A

4. Quick Check:

   Use <= for sequential logic assignments [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <=
• Ignoring sensitivity list importance
• Assuming initial values fix assignment errors

5.

You want to design a debouncer that waits for 10ms of stable input before changing output. The clock frequency is 1MHz. How many bits should the counter have at minimum?

hard

A. 14 bits

B. 10 bits

C. 20 bits

D. 8 bits

Solution

1. Step 1: Calculate required count for 10ms at 1MHz clock

   10ms = 0.01 seconds. Clock period = 1us (1/1MHz). Number of counts = 0.01 / 0.000001 = 10,000 counts.

2. Step 2: Find minimum bits to count 10,000

   2^13 = 8192 (too small), 2^14 = 16384 (enough). So minimum 14 bits needed.

3. Final Answer:

   14 bits -> Option A

4. Quick Check:

   10,000 < 2^14 = 16384 [OK]

Hint: Count = time * clock freq; bits = ceil(log2(count)) [OK]

Common Mistakes:

• Using clock frequency as count directly
• Choosing too few bits to cover count
• Confusing ms and us units