Automatic result checking in Verilog - Step-by-Step Execution

Concept Flow - Automatic result checking

Start Testbench

↓

Apply Inputs

↓

Run DUT (Design Under Test)

↓

Capture DUT Output

↓

Compare Output with Expected

↓

Match

↓

Pass Msg

↓

End Testbench

The testbench applies inputs to the design, captures outputs, compares them to expected results, and reports pass or error messages.

Execution Sample

Verilog

initial begin
  input_signal = 0;
  expected = 0;
  #10 input_signal = 1;
  expected = 1;
  #1 if (output_signal !== expected) $display("Error");
  #9 if (output_signal !== expected) $display("Error");
end

This code applies inputs over time and checks if the output matches the expected value, printing an error if not.

Execution Table

Step	Time (ns)	Input Signal	Output Signal	Expected Output	Comparison	Action
1	0	0	x	0	Unknown (output not ready)	Wait
2	10	1	0	1	Mismatch	Print Error: output 0 != expected 1
3	20	1	1	1	Match	No error, test passes

💡 Test ends after final comparison at 20 ns

Variable Tracker

Variable	Start (0 ns)	After 10 ns	After 20 ns
input_signal	0	1	1
output_signal	x (unknown)	0	1
expected	0	1	1

Key Moments - 3 Insights

Why is the output signal 'x' at time 0 ns?

At 0 ns, the DUT has not processed the input yet, so the output is unknown (x), as shown in execution_table row 1.

Why does the error print at 10 ns?

At 10 ns, input_signal changes to 1 but output_signal is still 0, which does not match expected 1, causing the error message in execution_table row 2.

When does the output match the expected value?

At 20 ns, output_signal updates to 1 matching expected 1, so no error is printed, as shown in execution_table row 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of output_signal at 10 ns?

A 0

B 1

C x (unknown)

D Does not exist

💡 Hint

Check the 'Output Signal' column at time 10 ns in execution_table row 2.

At which time does the comparison show a mismatch?

A 0 ns

B 20 ns

C 10 ns

D Never

💡 Hint

Look at the 'Comparison' column in execution_table to find where 'Mismatch' occurs.

If input_signal stayed 0 at 10 ns, what would happen to the error message?

A Error would still print at 10 ns

B No error would print at 10 ns

C Error would print at 20 ns instead

D Testbench would stop immediately

💡 Hint

Refer to variable_tracker and execution_table to see how input affects output and error printing.

Concept Snapshot

Automatic result checking in Verilog testbenches:
- Apply inputs to DUT over time
- Capture DUT outputs
- Compare outputs with expected values
- Print pass or error messages
- Use timing (# delays) to control input changes
- Helps catch design errors automatically

Full Transcript

In Verilog automatic result checking, the testbench applies inputs to the design under test (DUT) at specific times. The DUT processes these inputs and produces outputs. The testbench captures these outputs and compares them to expected values. If the output matches the expected value, the test passes silently. If there is a mismatch, the testbench prints an error message. This process repeats over simulation time, allowing automatic verification of the design's correctness. For example, at time 0 ns, the output is unknown because the DUT has not processed inputs yet. At 10 ns, the input changes but output does not match expected, so an error is printed. At 20 ns, output matches expected and no error occurs. This method helps catch bugs early and makes testing easier and more reliable.

Practice

1.

What is the main purpose of automatic result checking in a Verilog testbench?

easy

A. To compare actual output with expected output automatically

B. To manually inspect waveforms after simulation

C. To generate synthesis reports

D. To optimize the hardware design

Solution

1. Step 1: Understand the role of automatic checking

   Automatic result checking is used to verify if the design output matches the expected output during simulation.

2. Step 2: Identify the correct purpose

   It helps catch errors quickly by comparing outputs automatically, not manually inspecting or optimizing hardware.

3. Final Answer:

   To compare actual output with expected output automatically -> Option A

4. Quick Check:

   Automatic checking = Compare outputs [OK]

Hint: Automatic checking means comparing outputs without manual steps [OK]

Common Mistakes:

• Confusing automatic checking with manual waveform inspection
• Thinking it generates synthesis reports
• Assuming it optimizes hardware design

2.

Which Verilog operator is best to use for safe comparison of actual and expected values in automatic result checking?

easy

A. ==

B. !=

C. !==

D. ===

Solution

1. Step 1: Recall comparison operators in Verilog

   == and != do logical comparison but do not check for unknown (x) or high-impedance (z) states safely.

2. Step 2: Identify safe comparison operator

   === and !== are case equality operators that consider x and z states. For checking inequality safely, !== is preferred.

3. Final Answer:

   !== -> Option C

4. Quick Check:

   Safe comparison operator = !== [OK]

Hint: Use !== to catch unknown or high-impedance mismatches [OK]

Common Mistakes:

• Using == which ignores unknown states
• Confusing === with !==
• Using != which is unsafe for x or z

3.

What will be the output of this Verilog snippet during simulation?

reg [3:0] actual = 4'b1010;
reg [3:0] expected = 4'b1011;
initial begin
  if (actual !== expected)
    $display("Mismatch detected: actual=%b, expected=%b", actual, expected);
  else
    $display("Match");
end

medium

A. Syntax error

B. Match

C. No output

D. Mismatch detected: actual=1010, expected=1011

Solution

1. Step 1: Compare actual and expected values

   actual is 1010 and expected is 1011, so they differ in the last bit.

2. Step 2: Evaluate the if condition with !== operator

   Since actual !== expected is true, the $display inside the if block runs, printing the mismatch message.

3. Final Answer:

   Mismatch detected: actual=1010, expected=1011 -> Option D

4. Quick Check:

   Different values trigger mismatch message [OK]

Hint: If actual differs from expected, $display mismatch message [OK]

Common Mistakes:

• Assuming === works like == and prints Match
• Expecting no output when values differ
• Thinking syntax error occurs due to $display

4.

Identify the error in this Verilog testbench snippet for automatic result checking:

reg [7:0] actual, expected;
initial begin
  actual = 8'hFF;
  expected = 8'hFF;
  if (actual = expected)
    $display("Outputs match");
  else
    $display("Outputs differ");
end

medium

A. Incorrect register size

B. Using single = instead of comparison operator

C. Missing semicolon after $display

D. No initial block

Solution

1. Step 1: Check the if condition syntax

   The condition uses single = which is assignment, not comparison.

2. Step 2: Correct operator for comparison

   Use == or === for comparison, not = which causes a syntax or logic error.

3. Final Answer:

   Using single = instead of comparison operator -> Option B

4. Quick Check:

   Comparison needs == or ===, not = [OK]

Hint: Use == or === for comparison, not = assignment [OK]

Common Mistakes:

• Confusing = with == in if conditions
• Ignoring missing semicolons (which are present here)
• Assuming register size causes error

5.

You want to automatically check multiple outputs in a Verilog testbench and report all mismatches at once. Which approach is best?

1) Use multiple if statements with $display inside each
2) Use a loop to compare arrays of actual and expected values
3) Use a single if with combined conditions
4) Use synthesis directives to check outputs

hard

A. Use a loop to compare arrays of actual and expected values

B. Use multiple if statements with $display inside each

C. Use a single if with combined conditions

D. Use synthesis directives to check outputs

Solution

1. Step 1: Consider scalability of checking multiple outputs

   Multiple if statements become repetitive and hard to maintain for many outputs.

2. Step 2: Use a loop to automate comparisons

   Looping through arrays of actual and expected values allows automatic, scalable checking and reporting.

3. Step 3: Exclude synthesis directives

   Synthesis directives are for hardware synthesis, not simulation checking.

4. Final Answer:

   Use a loop to compare arrays of actual and expected values -> Option A

5. Quick Check:

   Looping arrays = scalable automatic checking [OK]

Hint: Loop through outputs to check all automatically [OK]

Common Mistakes:

• Using many separate if statements instead of a loop
• Combining all conditions in one if causing unclear errors
• Confusing synthesis directives with simulation checks