Automatic result checking in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of automatic result checking with simple comparator

What is the output of this Verilog testbench snippet that compares expected and actual results automatically?

module test;
  reg [3:0] expected = 4'b1010;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

Verilog

module test;
  reg [3:0] expected = 4'b1010;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

A No output

B FAIL

C Syntax error

D PASS

💡 Hint

Check if the expected and actual values are exactly the same using the === operator.

The === operator in Verilog checks for exact equality including X and Z states. Since expected and actual are both 4'b1010, the condition is true and "PASS" is printed.

❓ Predict Output

intermediate

Result of automatic checking with mismatch

What will this Verilog code print when actual does not match expected?

module test;
  reg [3:0] expected = 4'b1100;
  reg [3:0] actual = 4'b1000;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

Verilog

module test;
  reg [3:0] expected = 4'b1100;
  reg [3:0] actual = 4'b1000;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

A PASS

B FAIL

C Simulation error

D No output

💡 Hint

Compare the bits of expected and actual carefully.

Since expected is 1100 and actual is 1000, they differ in the second bit. The === operator returns false, so "FAIL" is printed.

🔧 Debug

advanced

Identify the error in automatic result checking code

This Verilog code is intended to automatically check if actual matches expected and print the result. What error will it cause?

module test;
  reg [3:0] expected = 4'b1010;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected = actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

Verilog

module test;
  reg [3:0] expected = 4'b1010;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected = actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

A Syntax error: unexpected '=' in if condition

B Always prints PASS

C Always prints FAIL

D No output

💡 Hint

Check the difference between assignment and comparison operators in conditions.

The code uses '=' (assignment) instead of '==' or '===' (comparison) in the if condition, which is a syntax error in Verilog.

❓ Predict Output

advanced

Output of automatic checking with unknown bits

What will this Verilog code print when expected has unknown bits (X)?

module test;
  reg [3:0] expected = 4'b10X0;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

Verilog

module test;
  reg [3:0] expected = 4'b10X0;
  reg [3:0] actual = 4'b1010;
  initial begin
    if (expected === actual) $display("PASS");
    else $display("FAIL");
  end
endmodule

A FAIL

B No output

C Simulation error

D PASS

💡 Hint

The === operator compares unknown bits strictly.

The expected value has an X bit, so expected === actual is false because actual has a 1 in that bit. The code prints "FAIL".

🧠 Conceptual

expert

Best practice for automatic result checking in Verilog testbenches

Which of the following is the best practice for automatic result checking in Verilog testbenches to ensure reliable verification?

A Use the == operator to compare expected and actual values ignoring unknown bits

B Manually print expected and actual values and visually inspect them

C Use the === operator to compare expected and actual values including unknown bits

D Use blocking assignments (=) inside always blocks for checking results

💡 Hint

Consider how unknown bits affect comparison results.

Using the === operator ensures that unknown (X) and high-impedance (Z) bits are compared exactly, which is important for reliable automatic checking.

Practice

1.

What is the main purpose of automatic result checking in a Verilog testbench?

easy

A. To compare actual output with expected output automatically

B. To manually inspect waveforms after simulation

C. To generate synthesis reports

D. To optimize the hardware design

Solution

1. Step 1: Understand the role of automatic checking

   Automatic result checking is used to verify if the design output matches the expected output during simulation.

2. Step 2: Identify the correct purpose

   It helps catch errors quickly by comparing outputs automatically, not manually inspecting or optimizing hardware.

3. Final Answer:

   To compare actual output with expected output automatically -> Option A

4. Quick Check:

   Automatic checking = Compare outputs [OK]

Hint: Automatic checking means comparing outputs without manual steps [OK]

Common Mistakes:

• Confusing automatic checking with manual waveform inspection
• Thinking it generates synthesis reports
• Assuming it optimizes hardware design

2.

Which Verilog operator is best to use for safe comparison of actual and expected values in automatic result checking?

easy

A. ==

B. !=

C. !==

D. ===

Solution

1. Step 1: Recall comparison operators in Verilog

   == and != do logical comparison but do not check for unknown (x) or high-impedance (z) states safely.

2. Step 2: Identify safe comparison operator

   === and !== are case equality operators that consider x and z states. For checking inequality safely, !== is preferred.

3. Final Answer:

   !== -> Option C

4. Quick Check:

   Safe comparison operator = !== [OK]

Hint: Use !== to catch unknown or high-impedance mismatches [OK]

Common Mistakes:

• Using == which ignores unknown states
• Confusing === with !==
• Using != which is unsafe for x or z

3.

What will be the output of this Verilog snippet during simulation?

reg [3:0] actual = 4'b1010;
reg [3:0] expected = 4'b1011;
initial begin
  if (actual !== expected)
    $display("Mismatch detected: actual=%b, expected=%b", actual, expected);
  else
    $display("Match");
end

medium

A. Syntax error

B. Match

C. No output

D. Mismatch detected: actual=1010, expected=1011

Solution

1. Step 1: Compare actual and expected values

   actual is 1010 and expected is 1011, so they differ in the last bit.

2. Step 2: Evaluate the if condition with !== operator

   Since actual !== expected is true, the $display inside the if block runs, printing the mismatch message.

3. Final Answer:

   Mismatch detected: actual=1010, expected=1011 -> Option D

4. Quick Check:

   Different values trigger mismatch message [OK]

Hint: If actual differs from expected, $display mismatch message [OK]

Common Mistakes:

• Assuming === works like == and prints Match
• Expecting no output when values differ
• Thinking syntax error occurs due to $display

4.

Identify the error in this Verilog testbench snippet for automatic result checking:

reg [7:0] actual, expected;
initial begin
  actual = 8'hFF;
  expected = 8'hFF;
  if (actual = expected)
    $display("Outputs match");
  else
    $display("Outputs differ");
end

medium

A. Incorrect register size

B. Using single = instead of comparison operator

C. Missing semicolon after $display

D. No initial block

Solution

1. Step 1: Check the if condition syntax

   The condition uses single = which is assignment, not comparison.

2. Step 2: Correct operator for comparison

   Use == or === for comparison, not = which causes a syntax or logic error.

3. Final Answer:

   Using single = instead of comparison operator -> Option B

4. Quick Check:

   Comparison needs == or ===, not = [OK]

Hint: Use == or === for comparison, not = assignment [OK]

Common Mistakes:

• Confusing = with == in if conditions
• Ignoring missing semicolons (which are present here)
• Assuming register size causes error

5.

You want to automatically check multiple outputs in a Verilog testbench and report all mismatches at once. Which approach is best?

1) Use multiple if statements with $display inside each
2) Use a loop to compare arrays of actual and expected values
3) Use a single if with combined conditions
4) Use synthesis directives to check outputs

hard

A. Use a loop to compare arrays of actual and expected values

B. Use multiple if statements with $display inside each

C. Use a single if with combined conditions

D. Use synthesis directives to check outputs

Solution

1. Step 1: Consider scalability of checking multiple outputs

   Multiple if statements become repetitive and hard to maintain for many outputs.

2. Step 2: Use a loop to automate comparisons

   Looping through arrays of actual and expected values allows automatic, scalable checking and reporting.

3. Step 3: Exclude synthesis directives

   Synthesis directives are for hardware synthesis, not simulation checking.

4. Final Answer:

   Use a loop to compare arrays of actual and expected values -> Option A

5. Quick Check:

   Looping arrays = scalable automatic checking [OK]

Hint: Loop through outputs to check all automatically [OK]

Common Mistakes:

• Using many separate if statements instead of a loop
• Combining all conditions in one if causing unclear errors
• Confusing synthesis directives with simulation checks