Automatic result checking in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a wire named 'result' that holds 8 bits.

Verilog

wire [7:0] [1] ;

Drag options to blanks, or click blank then click option'

Ainput

Breg

Coutput

Dresult

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'input' or 'output' keywords instead of a wire name.

Using 'reg' instead of 'wire' for a continuous assignment.

The wire named 'result' is declared with 8 bits using wire [7:0] result;.

2fill in blank

medium

Complete the code to assign the sum of 'a' and 'b' to 'result'.

Verilog

assign [1] = a + b;

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Aresult

Btemp

Coutput

Dsum

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning to a variable not declared as a wire.

Using a wrong variable name like 'sum' or 'temp'.

The continuous assignment uses assign result = a + b; to update 'result' automatically.

3fill in blank

hard

Fix the error in the always block sensitivity list to check changes on 'a' or 'b'.

Verilog

always @([1]) begin
  result <= a + b;
end

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Aa and b

Ba or b

Cposedge a or posedge b

Dnegedge a or negedge b

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'and' instead of 'or' in sensitivity list.

Using edge triggers when not required.

The sensitivity list should use a or b to trigger the block when either changes.

4fill in blank

hard

Fill both blanks to create a testbench that checks if 'result' equals the sum of 'a' and 'b'.

Verilog

initial begin
  a = 5; b = 3;
  #10;
  if (result [1] (a + b))
    $display("Test passed");
  else
    $display("Test failed");
end

Drag options to blanks, or click blank then click option'

A==

B!=

C>

D<

Attempts:

3 left

💡 Hint

Common Mistakes

Using '!=' instead of '==' causing wrong test results.

Using '>' or '<' which do not check equality.

The testbench uses if (result == (a + b)) to check if the result matches the expected sum.

5fill in blank

hard

Fill all three blanks to complete the automatic checking block that reports success or failure.

Verilog

always @(posedge clk) begin
  if ([1] == [2]) begin
    $display("[3]: Success");
  end else begin
    $display("[3]: Failure");
  end
end

Drag options to blanks, or click blank then click option'

Aresult

Bexpected

CTestbench

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Comparing wrong signals or variables.

Using inconsistent labels in display messages.

The block compares result with expected and prints Testbench status messages.

Practice

1.

What is the main purpose of automatic result checking in a Verilog testbench?

easy

A. To compare actual output with expected output automatically

B. To manually inspect waveforms after simulation

C. To generate synthesis reports

D. To optimize the hardware design

Solution

1. Step 1: Understand the role of automatic checking

   Automatic result checking is used to verify if the design output matches the expected output during simulation.

2. Step 2: Identify the correct purpose

   It helps catch errors quickly by comparing outputs automatically, not manually inspecting or optimizing hardware.

3. Final Answer:

   To compare actual output with expected output automatically -> Option A

4. Quick Check:

   Automatic checking = Compare outputs [OK]

Hint: Automatic checking means comparing outputs without manual steps [OK]

Common Mistakes:

• Confusing automatic checking with manual waveform inspection
• Thinking it generates synthesis reports
• Assuming it optimizes hardware design

2.

Which Verilog operator is best to use for safe comparison of actual and expected values in automatic result checking?

easy

A. ==

B. !=

C. !==

D. ===

Solution

1. Step 1: Recall comparison operators in Verilog

   == and != do logical comparison but do not check for unknown (x) or high-impedance (z) states safely.

2. Step 2: Identify safe comparison operator

   === and !== are case equality operators that consider x and z states. For checking inequality safely, !== is preferred.

3. Final Answer:

   !== -> Option C

4. Quick Check:

   Safe comparison operator = !== [OK]

Hint: Use !== to catch unknown or high-impedance mismatches [OK]

Common Mistakes:

• Using == which ignores unknown states
• Confusing === with !==
• Using != which is unsafe for x or z

3.

What will be the output of this Verilog snippet during simulation?

reg [3:0] actual = 4'b1010;
reg [3:0] expected = 4'b1011;
initial begin
  if (actual !== expected)
    $display("Mismatch detected: actual=%b, expected=%b", actual, expected);
  else
    $display("Match");
end

medium

A. Syntax error

B. Match

C. No output

D. Mismatch detected: actual=1010, expected=1011

Solution

1. Step 1: Compare actual and expected values

   actual is 1010 and expected is 1011, so they differ in the last bit.

2. Step 2: Evaluate the if condition with !== operator

   Since actual !== expected is true, the $display inside the if block runs, printing the mismatch message.

3. Final Answer:

   Mismatch detected: actual=1010, expected=1011 -> Option D

4. Quick Check:

   Different values trigger mismatch message [OK]

Hint: If actual differs from expected, $display mismatch message [OK]

Common Mistakes:

• Assuming === works like == and prints Match
• Expecting no output when values differ
• Thinking syntax error occurs due to $display

4.

Identify the error in this Verilog testbench snippet for automatic result checking:

reg [7:0] actual, expected;
initial begin
  actual = 8'hFF;
  expected = 8'hFF;
  if (actual = expected)
    $display("Outputs match");
  else
    $display("Outputs differ");
end

medium

A. Incorrect register size

B. Using single = instead of comparison operator

C. Missing semicolon after $display

D. No initial block

Solution

1. Step 1: Check the if condition syntax

   The condition uses single = which is assignment, not comparison.

2. Step 2: Correct operator for comparison

   Use == or === for comparison, not = which causes a syntax or logic error.

3. Final Answer:

   Using single = instead of comparison operator -> Option B

4. Quick Check:

   Comparison needs == or ===, not = [OK]

Hint: Use == or === for comparison, not = assignment [OK]

Common Mistakes:

• Confusing = with == in if conditions
• Ignoring missing semicolons (which are present here)
• Assuming register size causes error

5.

You want to automatically check multiple outputs in a Verilog testbench and report all mismatches at once. Which approach is best?

1) Use multiple if statements with $display inside each
2) Use a loop to compare arrays of actual and expected values
3) Use a single if with combined conditions
4) Use synthesis directives to check outputs

hard

A. Use a loop to compare arrays of actual and expected values

B. Use multiple if statements with $display inside each

C. Use a single if with combined conditions

D. Use synthesis directives to check outputs

Solution

1. Step 1: Consider scalability of checking multiple outputs

   Multiple if statements become repetitive and hard to maintain for many outputs.

2. Step 2: Use a loop to automate comparisons

   Looping through arrays of actual and expected values allows automatic, scalable checking and reporting.

3. Step 3: Exclude synthesis directives

   Synthesis directives are for hardware synthesis, not simulation checking.

4. Final Answer:

   Use a loop to compare arrays of actual and expected values -> Option A

5. Quick Check:

   Looping arrays = scalable automatic checking [OK]

Hint: Loop through outputs to check all automatically [OK]

Common Mistakes:

• Using many separate if statements instead of a loop
• Combining all conditions in one if causing unclear errors
• Confusing synthesis directives with simulation checks