Automatic result checking in Verilog - Mini Project: Build & Apply

Automatic Result Checking in Verilog Testbench

📖 Scenario: You are testing a simple 4-bit adder module in Verilog. To make sure your adder works correctly, you want to automatically check the output results against expected sums during simulation.

🎯 Goal: Build a Verilog testbench that applies inputs to the adder, automatically checks the output sum, and prints a message indicating if the output is correct or not.

📋 What You'll Learn

Create a 4-bit adder module instance with inputs a, b and output sum

Define test input vectors a and b with specific values

Create an expected result variable expected_sum for comparison

Use an always block or initial block to compare sum and expected_sum automatically

Print a message indicating PASS or FAIL for each test case

💡 Why This Matters

🌍 Real World

Automatic result checking helps engineers quickly verify hardware designs during simulation without manually inspecting waveforms.

💼 Career

Hardware engineers and verification engineers use automatic checking to improve productivity and reduce errors in chip design testing.

1

Create the 4-bit adder inputs and outputs

Declare reg [3:0] a and b as inputs, and wire [3:0] sum as output in your testbench.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
// Your code here

Hint

Use reg for inputs you will drive, and wire for outputs from the adder.

2

Add expected sum variable and instantiate the adder module

Declare a reg [3:0] expected_sum variable and instantiate the adder module named adder_inst connecting a, b, and sum.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
reg [3:0] expected_sum;

// Instantiate the adder module here
// Your code here

Hint

Use the module name adder and instance name adder_inst.

3

Apply test inputs and set expected sums

Inside an initial block, assign a = 4'd3, b = 4'd5, and expected_sum = 4'd8. Then wait for 10 time units.

Verilog

reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
reg [3:0] expected_sum;

adder adder_inst(.a(a), .b(b), .sum(sum));

initial begin
    // Your code here
end

Hint

Use delay #10; to wait for the adder output to settle.

4

Automatically check the result and print PASS or FAIL

After waiting, use an if statement to compare sum and expected_sum. Print "PASS: sum is correct" if equal, else print "FAIL: sum is incorrect".

Verilog

reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
reg [3:0] expected_sum;

adder adder_inst(.a(a), .b(b), .sum(sum));

initial begin
    a = 4'd3;
    b = 4'd5;
    expected_sum = 4'd8;
    #10;
    // Check sum and print result
    // Your code here
end

Hint

Use $display to print messages in Verilog.

Practice

1.

What is the main purpose of automatic result checking in a Verilog testbench?

easy

A. To compare actual output with expected output automatically

B. To manually inspect waveforms after simulation

C. To generate synthesis reports

D. To optimize the hardware design

Solution

1. Step 1: Understand the role of automatic checking

   Automatic result checking is used to verify if the design output matches the expected output during simulation.

2. Step 2: Identify the correct purpose

   It helps catch errors quickly by comparing outputs automatically, not manually inspecting or optimizing hardware.

3. Final Answer:

   To compare actual output with expected output automatically -> Option A

4. Quick Check:

   Automatic checking = Compare outputs [OK]

Hint: Automatic checking means comparing outputs without manual steps [OK]

Common Mistakes:

• Confusing automatic checking with manual waveform inspection
• Thinking it generates synthesis reports
• Assuming it optimizes hardware design

2.

Which Verilog operator is best to use for safe comparison of actual and expected values in automatic result checking?

easy

A. ==

B. !=

C. !==

D. ===

Solution

1. Step 1: Recall comparison operators in Verilog

   == and != do logical comparison but do not check for unknown (x) or high-impedance (z) states safely.

2. Step 2: Identify safe comparison operator

   === and !== are case equality operators that consider x and z states. For checking inequality safely, !== is preferred.

3. Final Answer:

   !== -> Option C

4. Quick Check:

   Safe comparison operator = !== [OK]

Hint: Use !== to catch unknown or high-impedance mismatches [OK]

Common Mistakes:

• Using == which ignores unknown states
• Confusing === with !==
• Using != which is unsafe for x or z

3.

What will be the output of this Verilog snippet during simulation?

reg [3:0] actual = 4'b1010;
reg [3:0] expected = 4'b1011;
initial begin
  if (actual !== expected)
    $display("Mismatch detected: actual=%b, expected=%b", actual, expected);
  else
    $display("Match");
end

medium

A. Syntax error

B. Match

C. No output

D. Mismatch detected: actual=1010, expected=1011

Solution

1. Step 1: Compare actual and expected values

   actual is 1010 and expected is 1011, so they differ in the last bit.

2. Step 2: Evaluate the if condition with !== operator

   Since actual !== expected is true, the $display inside the if block runs, printing the mismatch message.

3. Final Answer:

   Mismatch detected: actual=1010, expected=1011 -> Option D

4. Quick Check:

   Different values trigger mismatch message [OK]

Hint: If actual differs from expected, $display mismatch message [OK]

Common Mistakes:

• Assuming === works like == and prints Match
• Expecting no output when values differ
• Thinking syntax error occurs due to $display

4.

Identify the error in this Verilog testbench snippet for automatic result checking:

reg [7:0] actual, expected;
initial begin
  actual = 8'hFF;
  expected = 8'hFF;
  if (actual = expected)
    $display("Outputs match");
  else
    $display("Outputs differ");
end

medium

A. Incorrect register size

B. Using single = instead of comparison operator

C. Missing semicolon after $display

D. No initial block

Solution

1. Step 1: Check the if condition syntax

   The condition uses single = which is assignment, not comparison.

2. Step 2: Correct operator for comparison

   Use == or === for comparison, not = which causes a syntax or logic error.

3. Final Answer:

   Using single = instead of comparison operator -> Option B

4. Quick Check:

   Comparison needs == or ===, not = [OK]

Hint: Use == or === for comparison, not = assignment [OK]

Common Mistakes:

• Confusing = with == in if conditions
• Ignoring missing semicolons (which are present here)
• Assuming register size causes error

5.

You want to automatically check multiple outputs in a Verilog testbench and report all mismatches at once. Which approach is best?

1) Use multiple if statements with $display inside each
2) Use a loop to compare arrays of actual and expected values
3) Use a single if with combined conditions
4) Use synthesis directives to check outputs

hard

A. Use a loop to compare arrays of actual and expected values

B. Use multiple if statements with $display inside each

C. Use a single if with combined conditions

D. Use synthesis directives to check outputs

Solution

1. Step 1: Consider scalability of checking multiple outputs

   Multiple if statements become repetitive and hard to maintain for many outputs.

2. Step 2: Use a loop to automate comparisons

   Looping through arrays of actual and expected values allows automatic, scalable checking and reporting.

3. Step 3: Exclude synthesis directives

   Synthesis directives are for hardware synthesis, not simulation checking.

4. Final Answer:

   Use a loop to compare arrays of actual and expected values -> Option A

5. Quick Check:

   Looping arrays = scalable automatic checking [OK]

Hint: Loop through outputs to check all automatically [OK]

Common Mistakes:

• Using many separate if statements instead of a loop
• Combining all conditions in one if causing unclear errors
• Confusing synthesis directives with simulation checks