Verifying output with $finish in Verilog - Step-by-Step Execution

Concept Flow - Verifying output with $finish

Start simulation

↓

Run testbench code

↓

Display output with $display

↓

Call $finish to stop simulation

↓

Simulation ends cleanly

The simulation starts, runs testbench code, prints output using $display, then stops cleanly with $finish.

Execution Sample

Verilog

initial begin
  $display("Hello, simulation!");
  $finish;
end

always begin
  #5;
end

This code prints a message and then stops the simulation immediately.

Execution Table

Step	Action	Output	Simulation State
1	Start simulation		Running
2	$display prints message	Hello, simulation!	Running
3	$finish called		Stopping simulation
4	Simulation ends		Stopped

💡 $finish stops the simulation cleanly after output

Variable Tracker

Variable	Start	After $display	After $finish
simulation_state	Not started	Running	Stopped

Key Moments - 2 Insights

Why does the simulation stop after $finish is called?

Because $finish tells the simulator to end the simulation immediately, as shown in step 3 of the execution_table.

Does $display stop the simulation?

No, $display only prints output but the simulation continues until $finish is called, as seen between steps 2 and 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the simulation state after step 2?

A Not started

B Stopped

C Running

D Paused

💡 Hint

Check the 'Simulation State' column for step 2 in the execution_table.

At which step does the simulation stop?

A Step 1

B Step 4

C Step 3

D Step 2

💡 Hint

Look for when the simulation state changes to 'Stopped' in the execution_table.

If we remove $finish, what happens to the simulation?

A It runs forever or until manually stopped

B It stops immediately after $display

C It crashes

D It prints no output

💡 Hint

Refer to the key_moments about $finish stopping the simulation.

Concept Snapshot

initial begin
  $display("message");
  $finish;
end

always begin
  #5;
end

- $display prints output
- $finish stops simulation cleanly
- Without $finish, simulation keeps running

Full Transcript

This example shows how a Verilog simulation runs a testbench that prints a message using $display and then stops the simulation using $finish. The flow starts with the simulation running, then the message is printed, and finally $finish ends the simulation cleanly. The execution table tracks each step, showing the simulation state changes. Key points include that $display only prints output and does not stop the simulation, while $finish immediately stops it. If $finish is removed, the simulation would continue running indefinitely or until manually stopped.

Practice

1. What does the $finish command do in a Verilog simulation?

easy

A. Pauses the simulation temporarily

B. Stops the simulation immediately

C. Restarts the simulation from the beginning

D. Prints the current simulation time

Solution

1. Step 1: Understand the purpose of $finish

   The $finish command is used to stop the Verilog simulation immediately when called.

2. Step 2: Compare with other simulation commands

   Unlike $stop which pauses the simulation, $finish ends it completely.

3. Final Answer:

   Stops the simulation immediately -> Option B

4. Quick Check:

   $finish = stop simulation [OK]

Hint: Remember: $finish ends simulation, $stop pauses it [OK]

Common Mistakes:

• Confusing $finish with $stop
• Thinking $finish restarts simulation
• Assuming $finish only pauses simulation

2. Which of the following is the correct way to end a Verilog testbench simulation?

easy

A. $finish;

B. end_simulation;

C. finish();

D. $stop;

Solution

1. Step 1: Identify correct syntax for ending simulation

   In Verilog, $finish; is the correct system task to end simulation.

2. Step 2: Check other options for syntax errors

   $stop; pauses simulation, finish(); and end_simulation; are invalid syntax.

3. Final Answer:

   $finish; -> Option A

4. Quick Check:

   Correct syntax to end simulation = $finish; [OK]

Hint: Use $finish; with semicolon to end simulation [OK]

Common Mistakes:

• Using $stop; instead of $finish;
• Writing finish() like a function
• Missing semicolon after $finish

3. What will be the output of this Verilog code snippet?

initial begin
  $display("Start");
  $finish;
  $display("End");
end

medium

A. Start\nEnd

B. End

C. No output

D. Start

Solution

1. Step 1: Trace the code execution order

   The first $display prints "Start". Then $finish stops simulation immediately.

2. Step 2: Understand effect of $finish on following statements

   Because simulation ends at $finish, the second $display is never executed.

3. Final Answer:

   Start -> Option D

4. Quick Check:

   Output before $finish runs = Start [OK]

Hint: Code after $finish; does not run [OK]

Common Mistakes:

• Expecting output after $finish
• Confusing $finish with $stop
• Ignoring simulation stop effect

4. Identify the error in this Verilog testbench snippet:

initial begin
  $display("Test started");
  $finish
  $display("Test ended");
end

medium

A. Cannot use $finish inside initial block

B. Incorrect use of $display

C. Missing semicolon after $finish

D. No error, code is correct

Solution

1. Step 1: Check syntax of system tasks

   System tasks like $finish require a semicolon at the end.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after $finish, causing a syntax error.

3. Final Answer:

   Missing semicolon after $finish -> Option C

4. Quick Check:

   Always end $finish with semicolon [OK]

Hint: Always put semicolon after $finish [OK]

Common Mistakes:

• Omitting semicolon after $finish
• Thinking $finish can't be in initial block
• Misusing $display syntax

5. You want to run multiple tests in a Verilog testbench and stop simulation only after all tests finish. Which is the best way to use $finish?

hard

A. Call $finish at the end of the last test

B. Call $finish immediately after the first test

C. Call $finish inside every test block

D. Never use $finish to stop simulation

Solution

1. Step 1: Understand simulation flow for multiple tests

   Simulation should continue running until all tests complete to verify all outputs.

2. Step 2: Place $finish after last test

   Calling $finish after the last test ends simulation cleanly once all tests are done.

3. Final Answer:

   Call $finish at the end of the last test -> Option A

4. Quick Check:

   $finish after all tests = clean end [OK]

Hint: Use $finish once after all tests complete [OK]

Common Mistakes:

• Stopping simulation too early with $finish
• Calling $finish multiple times unnecessarily
• Avoiding $finish and letting simulation run forever