Verifying output with $finish in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog code snippet?

Consider the following Verilog testbench code. What will be printed before the simulation ends?

Verilog

module test;
  initial begin
    $display("Start of simulation");
    $finish;
    $display("This will not print");
  end
endmodule

A Start of simulation

B Start of simulation\nThis will not print

C This will not print

D No output

💡 Hint

Think about what $finish does in a simulation.

The $finish system task ends the simulation immediately. So, the second $display is never executed.

❓ Predict Output

intermediate

What happens if $finish is called inside a fork-join block?

Given this Verilog code, what output will appear before the simulation ends?

Verilog

module test;
  initial begin
    fork
      $display("Before finish");
      $finish;
      $display("After finish");
    join
  end
endmodule

A No output

B Before finish

C After finish

D Before finish\nAfter finish

💡 Hint

Remember that $finish stops the entire simulation immediately.

Even though the fork-join runs multiple threads, $finish stops the simulation immediately, so only the first $display runs.

🔧 Debug

advanced

Why does this Verilog code not print the last message?

Analyze the code below. Why is the last $display statement never printed?

Verilog

module test;
  initial begin
    $display("Message 1");
    #5 $finish;
    $display("Message 2");
  end
endmodule

A Because $finish only ends the current initial block, not the whole simulation

B Because $display("Message 2") is syntactically incorrect

C Because #5 delays the $display("Message 2") indefinitely

D Because $finish is called after 5 time units and ends simulation before Message 2 prints

💡 Hint

Think about the timing of $finish and when statements execute.

The #5 delay causes $finish to run after 5 time units, ending the simulation before the next $display can execute.

📝 Syntax

advanced

Identify the syntax error related to $finish usage

Which option contains a syntax error in using $finish in Verilog?

A initial $finish();

B always @(*) $finish;

C initial begin $finish; end

D initial begin $finish(); end

💡 Hint

Check the correct syntax for calling system tasks like $finish.

$finish is a system task and should be called without parentheses. Using parentheses causes a syntax error.

🚀 Application

expert

How many times does the $display print before simulation ends?

Consider this Verilog code. How many times will "Loop iteration" be printed before the simulation ends?

Verilog

module test;
  integer i;
  initial begin
    for (i = 0; i < 5; i = i + 1) begin
      $display("Loop iteration %0d", i);
      if (i == 2) $finish;
    end
  end
endmodule

A 2 times

B 5 times

C 3 times

D 0 times

💡 Hint

Think about when $finish stops the loop.

The loop prints for i=0,1,2. When i==2, $finish ends simulation immediately, so no further iterations.

Practice

1. What does the $finish command do in a Verilog simulation?

easy

A. Pauses the simulation temporarily

B. Stops the simulation immediately

C. Restarts the simulation from the beginning

D. Prints the current simulation time

Solution

1. Step 1: Understand the purpose of $finish

   The $finish command is used to stop the Verilog simulation immediately when called.

2. Step 2: Compare with other simulation commands

   Unlike $stop which pauses the simulation, $finish ends it completely.

3. Final Answer:

   Stops the simulation immediately -> Option B

4. Quick Check:

   $finish = stop simulation [OK]

Hint: Remember: $finish ends simulation, $stop pauses it [OK]

Common Mistakes:

• Confusing $finish with $stop
• Thinking $finish restarts simulation
• Assuming $finish only pauses simulation

2. Which of the following is the correct way to end a Verilog testbench simulation?

easy

A. $finish;

B. end_simulation;

C. finish();

D. $stop;

Solution

1. Step 1: Identify correct syntax for ending simulation

   In Verilog, $finish; is the correct system task to end simulation.

2. Step 2: Check other options for syntax errors

   $stop; pauses simulation, finish(); and end_simulation; are invalid syntax.

3. Final Answer:

   $finish; -> Option A

4. Quick Check:

   Correct syntax to end simulation = $finish; [OK]

Hint: Use $finish; with semicolon to end simulation [OK]

Common Mistakes:

• Using $stop; instead of $finish;
• Writing finish() like a function
• Missing semicolon after $finish

3. What will be the output of this Verilog code snippet?

initial begin
  $display("Start");
  $finish;
  $display("End");
end

medium

A. Start\nEnd

B. End

C. No output

D. Start

Solution

1. Step 1: Trace the code execution order

   The first $display prints "Start". Then $finish stops simulation immediately.

2. Step 2: Understand effect of $finish on following statements

   Because simulation ends at $finish, the second $display is never executed.

3. Final Answer:

   Start -> Option D

4. Quick Check:

   Output before $finish runs = Start [OK]

Hint: Code after $finish; does not run [OK]

Common Mistakes:

• Expecting output after $finish
• Confusing $finish with $stop
• Ignoring simulation stop effect

4. Identify the error in this Verilog testbench snippet:

initial begin
  $display("Test started");
  $finish
  $display("Test ended");
end

medium

A. Cannot use $finish inside initial block

B. Incorrect use of $display

C. Missing semicolon after $finish

D. No error, code is correct

Solution

1. Step 1: Check syntax of system tasks

   System tasks like $finish require a semicolon at the end.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after $finish, causing a syntax error.

3. Final Answer:

   Missing semicolon after $finish -> Option C

4. Quick Check:

   Always end $finish with semicolon [OK]

Hint: Always put semicolon after $finish [OK]

Common Mistakes:

• Omitting semicolon after $finish
• Thinking $finish can't be in initial block
• Misusing $display syntax

5. You want to run multiple tests in a Verilog testbench and stop simulation only after all tests finish. Which is the best way to use $finish?

hard

A. Call $finish at the end of the last test

B. Call $finish immediately after the first test

C. Call $finish inside every test block

D. Never use $finish to stop simulation

Solution

1. Step 1: Understand simulation flow for multiple tests

   Simulation should continue running until all tests complete to verify all outputs.

2. Step 2: Place $finish after last test

   Calling $finish after the last test ends simulation cleanly once all tests are done.

3. Final Answer:

   Call $finish at the end of the last test -> Option A

4. Quick Check:

   $finish after all tests = clean end [OK]

Hint: Use $finish once after all tests complete [OK]

Common Mistakes:

• Stopping simulation too early with $finish
• Calling $finish multiple times unnecessarily
• Avoiding $finish and letting simulation run forever