Verifying output with $finish in Verilog - Time & Space Complexity

Time Complexity: Verifying output with $finish

O(n)

Understanding Time Complexity

When we use $finish in Verilog, it stops the simulation. We want to see how long the simulation runs before it stops.

How does the number of steps before $finish change as input size grows?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module test;
  integer i;
  initial begin
    for (i = 0; i < 100; i = i + 1) begin
      $display("Count: %0d", i);
    end
    $finish;
  end
endmodule

This code counts from 0 to 99, printing each number, then stops the simulation with $finish.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The for loop that runs 100 times.
• How many times: Exactly 100 times before $finish stops the simulation.

How Execution Grows With Input

Explain the growth pattern intuitively.

Input Size (n)	Approx. Operations
10	10 loop steps
100	100 loop steps
1000	1000 loop steps

Pattern observation: The number of steps grows directly with the input size. Double the input, double the steps.

Final Time Complexity

Time Complexity: O(n)

This means the simulation time grows in a straight line as the input size increases.

Common Mistake

[X] Wrong: "The $finish command makes the simulation run instantly, so time complexity is constant."

[OK] Correct: $finish stops the simulation only after all loop steps run. The loop still takes time proportional to its size before $finish ends it.

Interview Connect

Understanding how $finish interacts with loops helps you reason about simulation time and testbench efficiency. This skill shows you can think about how code runs, not just what it does.

Self-Check

"What if we replaced the for loop with a nested loop? How would the time complexity change?"

Practice

1. What does the $finish command do in a Verilog simulation?

easy

A. Pauses the simulation temporarily

B. Stops the simulation immediately

C. Restarts the simulation from the beginning

D. Prints the current simulation time

Solution

1. Step 1: Understand the purpose of $finish

   The $finish command is used to stop the Verilog simulation immediately when called.

2. Step 2: Compare with other simulation commands

   Unlike $stop which pauses the simulation, $finish ends it completely.

3. Final Answer:

   Stops the simulation immediately -> Option B

4. Quick Check:

   $finish = stop simulation [OK]

Hint: Remember: $finish ends simulation, $stop pauses it [OK]

Common Mistakes:

• Confusing $finish with $stop
• Thinking $finish restarts simulation
• Assuming $finish only pauses simulation

2. Which of the following is the correct way to end a Verilog testbench simulation?

easy

A. $finish;

B. end_simulation;

C. finish();

D. $stop;

Solution

1. Step 1: Identify correct syntax for ending simulation

   In Verilog, $finish; is the correct system task to end simulation.

2. Step 2: Check other options for syntax errors

   $stop; pauses simulation, finish(); and end_simulation; are invalid syntax.

3. Final Answer:

   $finish; -> Option A

4. Quick Check:

   Correct syntax to end simulation = $finish; [OK]

Hint: Use $finish; with semicolon to end simulation [OK]

Common Mistakes:

• Using $stop; instead of $finish;
• Writing finish() like a function
• Missing semicolon after $finish

3. What will be the output of this Verilog code snippet?

initial begin
  $display("Start");
  $finish;
  $display("End");
end

medium

A. Start\nEnd

B. End

C. No output

D. Start

Solution

1. Step 1: Trace the code execution order

   The first $display prints "Start". Then $finish stops simulation immediately.

2. Step 2: Understand effect of $finish on following statements

   Because simulation ends at $finish, the second $display is never executed.

3. Final Answer:

   Start -> Option D

4. Quick Check:

   Output before $finish runs = Start [OK]

Hint: Code after $finish; does not run [OK]

Common Mistakes:

• Expecting output after $finish
• Confusing $finish with $stop
• Ignoring simulation stop effect

4. Identify the error in this Verilog testbench snippet:

initial begin
  $display("Test started");
  $finish
  $display("Test ended");
end

medium

A. Cannot use $finish inside initial block

B. Incorrect use of $display

C. Missing semicolon after $finish

D. No error, code is correct

Solution

1. Step 1: Check syntax of system tasks

   System tasks like $finish require a semicolon at the end.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after $finish, causing a syntax error.

3. Final Answer:

   Missing semicolon after $finish -> Option C

4. Quick Check:

   Always end $finish with semicolon [OK]

Hint: Always put semicolon after $finish [OK]

Common Mistakes:

• Omitting semicolon after $finish
• Thinking $finish can't be in initial block
• Misusing $display syntax

5. You want to run multiple tests in a Verilog testbench and stop simulation only after all tests finish. Which is the best way to use $finish?

hard

A. Call $finish at the end of the last test

B. Call $finish immediately after the first test

C. Call $finish inside every test block

D. Never use $finish to stop simulation

Solution

1. Step 1: Understand simulation flow for multiple tests

   Simulation should continue running until all tests complete to verify all outputs.

2. Step 2: Place $finish after last test

   Calling $finish after the last test ends simulation cleanly once all tests are done.

3. Final Answer:

   Call $finish at the end of the last test -> Option A

4. Quick Check:

   $finish after all tests = clean end [OK]

Hint: Use $finish once after all tests complete [OK]

Common Mistakes:

• Stopping simulation too early with $finish
• Calling $finish multiple times unnecessarily
• Avoiding $finish and letting simulation run forever