Verifying output with $finish in Verilog - Mini Project: Build & Apply

Verifying output with $finish

📖 Scenario: You are creating a simple Verilog testbench to check the output of a small module. You want to make sure the simulation stops after showing the results.

🎯 Goal: Build a Verilog testbench that prints a message and then stops the simulation using $finish.

📋 What You'll Learn

Create an initial block that prints a message using $display

Use $finish to stop the simulation after printing

Ensure the simulation output shows the message exactly as specified

💡 Why This Matters

🌍 Real World

In hardware design, testbenches use <code>$display</code> to show signals and <code>$finish</code> to stop simulation cleanly.

💼 Career

Knowing how to verify outputs and control simulation flow is essential for FPGA and ASIC design engineers.

1

Create initial block with a display message

Write an initial block that uses $display("Hello, Verilog!") to print the message.

Verilog

initial begin
    // Your code here
end

Hint

Use initial begin and $display to print the message once at the start.

2

Add $finish to stop simulation

Inside the same initial block, add $finish; after the $display statement to stop the simulation.

Verilog

initial begin
    $display("Hello, Verilog!");
    // Your code here
end

Hint

Place $finish; right after $display inside the initial block.

3

Add module wrapper for testbench

Create a module named testbench that contains the initial block with $display and $finish.

Verilog

module testbench;
    // Your code here
endmodule

Hint

Wrap the initial block inside module testbench and endmodule.

4

Run simulation and verify output

Run the simulation and print the output. Use $display to show the message and ensure the simulation stops with $finish. Write a line to print "Simulation complete" before $finish.

Verilog

module testbench;
    initial begin
        $display("Hello, Verilog!");
        // Your code here
    end
endmodule

Hint

Print the second message before calling $finish to see both messages in the output.

Practice

1. What does the $finish command do in a Verilog simulation?

easy

A. Pauses the simulation temporarily

B. Stops the simulation immediately

C. Restarts the simulation from the beginning

D. Prints the current simulation time

Solution

1. Step 1: Understand the purpose of $finish

   The $finish command is used to stop the Verilog simulation immediately when called.

2. Step 2: Compare with other simulation commands

   Unlike $stop which pauses the simulation, $finish ends it completely.

3. Final Answer:

   Stops the simulation immediately -> Option B

4. Quick Check:

   $finish = stop simulation [OK]

Hint: Remember: $finish ends simulation, $stop pauses it [OK]

Common Mistakes:

• Confusing $finish with $stop
• Thinking $finish restarts simulation
• Assuming $finish only pauses simulation

2. Which of the following is the correct way to end a Verilog testbench simulation?

easy

A. $finish;

B. end_simulation;

C. finish();

D. $stop;

Solution

1. Step 1: Identify correct syntax for ending simulation

   In Verilog, $finish; is the correct system task to end simulation.

2. Step 2: Check other options for syntax errors

   $stop; pauses simulation, finish(); and end_simulation; are invalid syntax.

3. Final Answer:

   $finish; -> Option A

4. Quick Check:

   Correct syntax to end simulation = $finish; [OK]

Hint: Use $finish; with semicolon to end simulation [OK]

Common Mistakes:

• Using $stop; instead of $finish;
• Writing finish() like a function
• Missing semicolon after $finish

3. What will be the output of this Verilog code snippet?

initial begin
  $display("Start");
  $finish;
  $display("End");
end

medium

A. Start\nEnd

B. End

C. No output

D. Start

Solution

1. Step 1: Trace the code execution order

   The first $display prints "Start". Then $finish stops simulation immediately.

2. Step 2: Understand effect of $finish on following statements

   Because simulation ends at $finish, the second $display is never executed.

3. Final Answer:

   Start -> Option D

4. Quick Check:

   Output before $finish runs = Start [OK]

Hint: Code after $finish; does not run [OK]

Common Mistakes:

• Expecting output after $finish
• Confusing $finish with $stop
• Ignoring simulation stop effect

4. Identify the error in this Verilog testbench snippet:

initial begin
  $display("Test started");
  $finish
  $display("Test ended");
end

medium

A. Cannot use $finish inside initial block

B. Incorrect use of $display

C. Missing semicolon after $finish

D. No error, code is correct

Solution

1. Step 1: Check syntax of system tasks

   System tasks like $finish require a semicolon at the end.

2. Step 2: Identify missing semicolon

   The code misses a semicolon after $finish, causing a syntax error.

3. Final Answer:

   Missing semicolon after $finish -> Option C

4. Quick Check:

   Always end $finish with semicolon [OK]

Hint: Always put semicolon after $finish [OK]

Common Mistakes:

• Omitting semicolon after $finish
• Thinking $finish can't be in initial block
• Misusing $display syntax

5. You want to run multiple tests in a Verilog testbench and stop simulation only after all tests finish. Which is the best way to use $finish?

hard

A. Call $finish at the end of the last test

B. Call $finish immediately after the first test

C. Call $finish inside every test block

D. Never use $finish to stop simulation

Solution

1. Step 1: Understand simulation flow for multiple tests

   Simulation should continue running until all tests complete to verify all outputs.

2. Step 2: Place $finish after last test

   Calling $finish after the last test ends simulation cleanly once all tests are done.

3. Final Answer:

   Call $finish at the end of the last test -> Option A

4. Quick Check:

   $finish after all tests = clean end [OK]

Hint: Use $finish once after all tests complete [OK]

Common Mistakes:

• Stopping simulation too early with $finish
• Calling $finish multiple times unnecessarily
• Avoiding $finish and letting simulation run forever