Signed vs unsigned representation in Verilog - Visual Side-by-Side Comparison

Concept Flow - Signed vs unsigned representation

Start

↓

Define number

↓

Is number signed?

Yes→Use two's complement

↓

Interpret bits as negative if MSB=1

↓

Interpret bits as positive

↓

Display value

↓

End

This flow shows how a number is interpreted differently based on whether it is signed or unsigned in Verilog.

Execution Sample

Verilog

module test;
  reg signed [3:0] a = 4'b1111;
  reg [3:0] b = 4'b1111;
  initial begin
    $display("a = %d, b = %d", a, b);
  end
endmodule

This code shows how the same 4-bit pattern is interpreted as signed and unsigned numbers.

Execution Table

Step	Variable	Bit Pattern	Interpretation	Value Displayed
1	a	1111	Signed (two's complement)	-1
2	b	1111	Unsigned (binary)	15
3	End	-	-	Execution stops after display

💡 Display completes and simulation ends.

Variable Tracker

Variable	Start	After Initialization	Final
a	undefined	1111 (signed)	-1
b	undefined	1111 (unsigned)	15

Key Moments - 2 Insights

Why does 'a' show -1 but 'b' shows 15 even though both have the same bits?

Because 'a' is declared signed, Verilog interprets the bits as two's complement, making 1111 equal to -1. 'b' is unsigned, so 1111 is 15 in decimal (see execution_table rows 1 and 2).

What does the most significant bit (MSB) represent in signed numbers?

In signed numbers, the MSB is the sign bit: 0 means positive, 1 means negative (two's complement). This is why 1111 is negative for 'a' (row 1).

Visual Quiz - 3 Questions

Look at the execution table, what is the decimal value of 'a' at step 1?

A -1

B 15

C 0

D 1

💡 Hint

Check the 'Value Displayed' column for variable 'a' at step 1.

At which step does the unsigned variable 'b' get its value interpreted?

A Step 1

B Step 2

C Step 3

D No step

💡 Hint

Look for variable 'b' in the 'Variable' column and see its interpretation step.

If 'a' was declared unsigned, what would its displayed value be at step 1?

A -1

B 0

C 15

D 1

💡 Hint

Refer to the value of 'b' which is unsigned with the same bits in the execution_table.

Concept Snapshot

Signed vs unsigned in Verilog:
- Signed numbers use two's complement.
- MSB is sign bit in signed numbers.
- Unsigned numbers are always positive.
- Same bits can mean different values.
- Declare with 'signed' keyword for signed.
- Use %d in $display for decimal output.

Full Transcript

This example shows how Verilog treats signed and unsigned numbers differently. The variable 'a' is signed 4-bit with bits 1111, which is -1 in two's complement. The variable 'b' is unsigned 4-bit with the same bits 1111, which is 15 in decimal. The flow starts by defining the number, checking if it is signed, then interpreting bits accordingly. The MSB acts as a sign bit for signed numbers. The display shows the difference clearly. This helps beginners understand how the same bits can represent different values depending on signedness.

Practice

1. Which of the following statements about signed and unsigned variables in Verilog is correct?

easy

A. Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers.

B. Unsigned variables can hold negative numbers, signed variables cannot.

C. Signed and unsigned variables behave the same in all calculations.

D. You declare unsigned variables using the signed keyword.

Solution

1. Step 1: Understand signed vs unsigned meaning

   Signed variables can represent negative and positive values, unsigned only positive values.

2. Step 2: Check declaration keywords

   Signed variables use the signed keyword; unsigned variables do not use it.

3. Final Answer:

   Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers. -> Option A

4. Quick Check:

   Signed = negative and positive [OK]

Hint: Signed means negative and positive; unsigned means only positive [OK]

Common Mistakes:

• Thinking unsigned can hold negative numbers
• Confusing declaration keywords
• Assuming signed and unsigned behave identically

2. Which is the correct way to declare a 8-bit signed variable in Verilog?

easy

A. reg [7:0] my_var;

B. reg signed my_var [7:0];

C. reg unsigned [7:0] my_var;

D. reg signed [7:0] my_var;

Solution

1. Step 1: Recall syntax for signed declaration

   In Verilog, signed variables are declared with the keyword signed before the bit range.

2. Step 2: Check each option's syntax

   reg signed [7:0] my_var; uses reg signed [7:0] my_var; which is correct syntax for an 8-bit signed variable.

3. Final Answer:

   reg signed [7:0] my_var; -> Option D

4. Quick Check:

   Signed keyword before bit range = correct [OK]

Hint: Use 'reg signed [bits]' to declare signed variables [OK]

Common Mistakes:

• Placing 'signed' after variable name
• Using 'unsigned' keyword which is invalid
• Omitting 'signed' keyword for signed variables

3. What is the decimal value of the 4-bit signed number 4'b1101 in Verilog?

medium

A. -3

B. 13

C. -11

D. 3

Solution

1. Step 1: Interpret 4-bit signed binary 1101

   In 4-bit signed, the leftmost bit is sign bit. 1 means negative. The value is two's complement.

2. Step 2: Calculate two's complement value

   Invert bits: 0010, add 1: 0011 (decimal 3). So original number is -3.

3. Final Answer:

   -3 -> Option A

4. Quick Check:

   4-bit signed 1101 = -3 [OK]

Hint: For signed, if MSB=1, find two's complement negative value [OK]

Common Mistakes:

• Reading binary as unsigned
• Ignoring two's complement for negative numbers
• Confusing bit order

4. Given the code snippet:

reg signed [3:0] a = 4'b1010;
reg [3:0] b = 4'b0101;
wire [4:0] sum = a + b;

What is the problem with this code?

medium

A. The variable 'a' should not be signed for addition.

B. You cannot add signed and unsigned variables directly without casting.

C. The wire 'sum' is declared with wrong bit width.

D. There is no problem; the code is correct.

Solution

1. Step 1: Identify variable types in addition

   Variable 'a' is signed, 'b' is unsigned. Adding signed and unsigned directly can cause unexpected results.

2. Step 2: Understand Verilog rules for mixed signed/unsigned

   Verilog treats unsigned as signed 0-extended or may cause wrong sign extension. Proper casting is needed.

3. Final Answer:

   You cannot add signed and unsigned variables directly without casting. -> Option B

4. Quick Check:

   Mixing signed and unsigned needs casting [OK]

Hint: Avoid mixing signed and unsigned without explicit casting [OK]

Common Mistakes:

• Ignoring signed/unsigned mismatch
• Assuming bit width is the only issue
• Thinking signed variables can't be added

5. You want to store the result of subtracting two 5-bit unsigned numbers a and b in a signed 6-bit variable diff. Which Verilog code correctly handles the signed result?

hard

A. reg signed [5:0] diff = a - b;

B. reg [5:0] diff = a - b;

C. reg signed [5:0] diff = $signed(a) - $signed(b);

D. reg signed [4:0] diff = a - b;

Solution

1. Step 1: Understand the problem of unsigned subtraction

   Subtracting unsigned numbers can produce negative results, so result must be signed and wide enough.

2. Step 2: Check casting and bit width

   reg signed [5:0] diff = $signed(a) - $signed(b); casts both operands to signed before subtraction and uses 6 bits for result, correctly handling negative values.

3. Final Answer:

   reg signed [5:0] diff = $signed(a) - $signed(b); -> Option C

4. Quick Check:

   Cast operands signed before subtracting unsigned numbers [OK]

Hint: Cast unsigned to signed before subtracting to get correct sign [OK]

Common Mistakes:

• Not casting operands to signed
• Using too few bits for result
• Assuming unsigned subtraction can yield negative