Signed vs unsigned representation in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of signed addition in Verilog

What is the output of the following Verilog code snippet when adding a signed and an unsigned 4-bit number?

Verilog

module test;
  reg signed [3:0] a = -3;
  reg [3:0] b = 4'd5;
  wire signed [4:0] sum;
  assign sum = a + b;
  initial begin
    $display("sum = %d", sum);
  end
endmodule

A sum = -8

B sum = 2

C sum = 8

D sum = 12

💡 Hint

Remember that signed and unsigned addition in Verilog extends the sign bit for signed numbers.

The signed number -3 is represented as 4'b1101. Adding 5 (4'b0101) results in 2 (5'b00010) when extended to 5 bits with sign extension.

❓ Predict Output

intermediate

Result of signed vs unsigned comparison

What is the output of this Verilog code comparing signed and unsigned values?

Verilog

module test;
  reg signed [3:0] a = -1;
  reg [3:0] b = 4'd15;
  initial begin
    if (a < b) $display("True"); else $display("False");
  end
endmodule

A Simulation error

B True

C False

D No output

💡 Hint

Consider how Verilog treats signed and unsigned comparisons.

In Verilog, when comparing signed and unsigned, the signed value is treated as unsigned, so -1 (4'b1111) is 15 unsigned, so a < b is false.

🔧 Debug

advanced

Identify the error in signed multiplication

Which option shows the correct way to multiply two signed 4-bit numbers in Verilog without losing sign information?

A wire signed [7:0] result = a * b;

B wire signed [3:0] result = a * b;

C wire [3:0] result = a * b;

D wire [7:0] result = a * b;

💡 Hint

Check the width and signedness of the result wire.

To preserve sign and avoid overflow, the result must be signed and wide enough (8 bits) to hold the product of two 4-bit signed numbers.

📝 Syntax

advanced

Syntax error in signed assignment

Which option will cause a syntax error in Verilog when assigning a signed value?

A reg [3:0] a; a = -4'd3;

B reg signed [3:0] a; a = -4'd3;

C reg signed [3:0] a; a = 4'd3;

D reg signed [3:0] a; a = 4'sd-3;

💡 Hint

Consider how negative values are assigned to unsigned registers.

Assigning a negative value to an unsigned reg (option A) causes a syntax error or unexpected behavior.

🚀 Application

expert

Predict the output of mixed signed/unsigned arithmetic

Given the following Verilog code, what is the output printed?

Verilog

module test;
  reg signed [3:0] a = -4'sd7;
  reg [3:0] b = 4'd9;
  wire signed [4:0] c;
  assign c = a + b;
  initial begin
    $display("c = %d", c);
  end
endmodule

A c = -7

B c = -16

C c = 18

D c = 2

💡 Hint

Remember sign extension rules when adding signed and unsigned numbers.

a is -7, b is 9, sum is 2. The signed wire c holds the correct signed result.

Practice

1. Which of the following statements about signed and unsigned variables in Verilog is correct?

easy

A. Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers.

B. Unsigned variables can hold negative numbers, signed variables cannot.

C. Signed and unsigned variables behave the same in all calculations.

D. You declare unsigned variables using the signed keyword.

Solution

1. Step 1: Understand signed vs unsigned meaning

   Signed variables can represent negative and positive values, unsigned only positive values.

2. Step 2: Check declaration keywords

   Signed variables use the signed keyword; unsigned variables do not use it.

3. Final Answer:

   Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers. -> Option A

4. Quick Check:

   Signed = negative and positive [OK]

Hint: Signed means negative and positive; unsigned means only positive [OK]

Common Mistakes:

• Thinking unsigned can hold negative numbers
• Confusing declaration keywords
• Assuming signed and unsigned behave identically

2. Which is the correct way to declare a 8-bit signed variable in Verilog?

easy

A. reg [7:0] my_var;

B. reg signed my_var [7:0];

C. reg unsigned [7:0] my_var;

D. reg signed [7:0] my_var;

Solution

1. Step 1: Recall syntax for signed declaration

   In Verilog, signed variables are declared with the keyword signed before the bit range.

2. Step 2: Check each option's syntax

   reg signed [7:0] my_var; uses reg signed [7:0] my_var; which is correct syntax for an 8-bit signed variable.

3. Final Answer:

   reg signed [7:0] my_var; -> Option D

4. Quick Check:

   Signed keyword before bit range = correct [OK]

Hint: Use 'reg signed [bits]' to declare signed variables [OK]

Common Mistakes:

• Placing 'signed' after variable name
• Using 'unsigned' keyword which is invalid
• Omitting 'signed' keyword for signed variables

3. What is the decimal value of the 4-bit signed number 4'b1101 in Verilog?

medium

A. -3

B. 13

C. -11

D. 3

Solution

1. Step 1: Interpret 4-bit signed binary 1101

   In 4-bit signed, the leftmost bit is sign bit. 1 means negative. The value is two's complement.

2. Step 2: Calculate two's complement value

   Invert bits: 0010, add 1: 0011 (decimal 3). So original number is -3.

3. Final Answer:

   -3 -> Option A

4. Quick Check:

   4-bit signed 1101 = -3 [OK]

Hint: For signed, if MSB=1, find two's complement negative value [OK]

Common Mistakes:

• Reading binary as unsigned
• Ignoring two's complement for negative numbers
• Confusing bit order

4. Given the code snippet:

reg signed [3:0] a = 4'b1010;
reg [3:0] b = 4'b0101;
wire [4:0] sum = a + b;

What is the problem with this code?

medium

A. The variable 'a' should not be signed for addition.

B. You cannot add signed and unsigned variables directly without casting.

C. The wire 'sum' is declared with wrong bit width.

D. There is no problem; the code is correct.

Solution

1. Step 1: Identify variable types in addition

   Variable 'a' is signed, 'b' is unsigned. Adding signed and unsigned directly can cause unexpected results.

2. Step 2: Understand Verilog rules for mixed signed/unsigned

   Verilog treats unsigned as signed 0-extended or may cause wrong sign extension. Proper casting is needed.

3. Final Answer:

   You cannot add signed and unsigned variables directly without casting. -> Option B

4. Quick Check:

   Mixing signed and unsigned needs casting [OK]

Hint: Avoid mixing signed and unsigned without explicit casting [OK]

Common Mistakes:

• Ignoring signed/unsigned mismatch
• Assuming bit width is the only issue
• Thinking signed variables can't be added

5. You want to store the result of subtracting two 5-bit unsigned numbers a and b in a signed 6-bit variable diff. Which Verilog code correctly handles the signed result?

hard

A. reg signed [5:0] diff = a - b;

B. reg [5:0] diff = a - b;

C. reg signed [5:0] diff = $signed(a) - $signed(b);

D. reg signed [4:0] diff = a - b;

Solution

1. Step 1: Understand the problem of unsigned subtraction

   Subtracting unsigned numbers can produce negative results, so result must be signed and wide enough.

2. Step 2: Check casting and bit width

   reg signed [5:0] diff = $signed(a) - $signed(b); casts both operands to signed before subtraction and uses 6 bits for result, correctly handling negative values.

3. Final Answer:

   reg signed [5:0] diff = $signed(a) - $signed(b); -> Option C

4. Quick Check:

   Cast operands signed before subtracting unsigned numbers [OK]

Hint: Cast unsigned to signed before subtracting to get correct sign [OK]

Common Mistakes:

• Not casting operands to signed
• Using too few bits for result
• Assuming unsigned subtraction can yield negative