Signed vs unsigned representation in Verilog - Hands-On Comparison

Signed vs unsigned representation

📖 Scenario: You are working with digital signals in hardware design. Sometimes numbers can be positive or negative (signed), and sometimes only positive (unsigned). Understanding how to represent and use signed and unsigned numbers in Verilog is important for correct calculations.

🎯 Goal: You will create a simple Verilog module that declares signed and unsigned 4-bit numbers, assigns values to them, and then outputs their sum and difference to see how signed and unsigned representations affect the results.

📋 What You'll Learn

Declare a 4-bit unsigned register called a and assign it the value 9

Declare a 4-bit signed register called b and assign it the value -3

Create a 5-bit signed wire called sum that adds a and b

Create a 5-bit signed wire called diff that subtracts b from a

Display the values of a, b, sum, and diff using $display

💡 Why This Matters

🌍 Real World

In hardware design, signals can represent positive or negative numbers. Correctly using signed and unsigned types ensures your circuits behave as expected when performing arithmetic.

💼 Career

Understanding signed vs unsigned representation is essential for FPGA and ASIC designers, verification engineers, and anyone working with digital logic and hardware description languages like Verilog.

1

Declare unsigned and signed registers

Declare a 4-bit unsigned register called a and assign it the value 9. Also declare a 4-bit signed register called b and assign it the value -3.

Verilog

module signed_unsigned_demo();

// Declare 4-bit unsigned register 'a' with value 9
// Declare 4-bit signed register 'b' with value -3

endmodule

Hint

Use reg [3:0] a = 4'd9; for unsigned and reg signed [3:0] b = -4'sd3; for signed.

2

Create signed wires for sum and difference

Create a 5-bit signed wire called sum that adds a and b. Also create a 5-bit signed wire called diff that subtracts b from a.

Verilog

module signed_unsigned_demo();

reg [3:0] a = 4'd9;
reg signed [3:0] b = -4'sd3;

// Declare 5-bit signed wire 'sum' as a + b
// Declare 5-bit signed wire 'diff' as a - b

endmodule

Hint

Use wire signed [4:0] sum = a + b; and wire signed [4:0] diff = a - b;.

3

Add initial block to display values

Add an initial block that uses $display to print the values of a, b, sum, and diff. Use %d format specifier for decimal output.

Verilog

module signed_unsigned_demo();

reg [3:0] a = 4'd9;
reg signed [3:0] b = -4'sd3;

wire signed [4:0] sum = a + b;
wire signed [4:0] diff = a - b;

initial begin
    // Display values of a, b, sum, and diff
end

endmodule

Hint

Use an initial block with $display statements for each variable.

4

Run simulation and observe output

Run the simulation and observe the printed output showing the values of a, b, sum, and diff. The output should be exactly:
a (unsigned) = 9
b (signed) = -3
sum (signed) = 6
diff (signed) = 12

Verilog

module signed_unsigned_demo();

reg [3:0] a = 4'd9;
reg signed [3:0] b = -4'sd3;

wire signed [4:0] sum = a + b;
wire signed [4:0] diff = a - b;

initial begin
    // Run simulation and observe output
end

endmodule

Hint

Run the simulation to see the output values printed exactly as shown.

Practice

1. Which of the following statements about signed and unsigned variables in Verilog is correct?

easy

A. Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers.

B. Unsigned variables can hold negative numbers, signed variables cannot.

C. Signed and unsigned variables behave the same in all calculations.

D. You declare unsigned variables using the signed keyword.

Solution

1. Step 1: Understand signed vs unsigned meaning

   Signed variables can represent negative and positive values, unsigned only positive values.

2. Step 2: Check declaration keywords

   Signed variables use the signed keyword; unsigned variables do not use it.

3. Final Answer:

   Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers. -> Option A

4. Quick Check:

   Signed = negative and positive [OK]

Hint: Signed means negative and positive; unsigned means only positive [OK]

Common Mistakes:

• Thinking unsigned can hold negative numbers
• Confusing declaration keywords
• Assuming signed and unsigned behave identically

2. Which is the correct way to declare a 8-bit signed variable in Verilog?

easy

A. reg [7:0] my_var;

B. reg signed my_var [7:0];

C. reg unsigned [7:0] my_var;

D. reg signed [7:0] my_var;

Solution

1. Step 1: Recall syntax for signed declaration

   In Verilog, signed variables are declared with the keyword signed before the bit range.

2. Step 2: Check each option's syntax

   reg signed [7:0] my_var; uses reg signed [7:0] my_var; which is correct syntax for an 8-bit signed variable.

3. Final Answer:

   reg signed [7:0] my_var; -> Option D

4. Quick Check:

   Signed keyword before bit range = correct [OK]

Hint: Use 'reg signed [bits]' to declare signed variables [OK]

Common Mistakes:

• Placing 'signed' after variable name
• Using 'unsigned' keyword which is invalid
• Omitting 'signed' keyword for signed variables

3. What is the decimal value of the 4-bit signed number 4'b1101 in Verilog?

medium

A. -3

B. 13

C. -11

D. 3

Solution

1. Step 1: Interpret 4-bit signed binary 1101

   In 4-bit signed, the leftmost bit is sign bit. 1 means negative. The value is two's complement.

2. Step 2: Calculate two's complement value

   Invert bits: 0010, add 1: 0011 (decimal 3). So original number is -3.

3. Final Answer:

   -3 -> Option A

4. Quick Check:

   4-bit signed 1101 = -3 [OK]

Hint: For signed, if MSB=1, find two's complement negative value [OK]

Common Mistakes:

• Reading binary as unsigned
• Ignoring two's complement for negative numbers
• Confusing bit order

4. Given the code snippet:

reg signed [3:0] a = 4'b1010;
reg [3:0] b = 4'b0101;
wire [4:0] sum = a + b;

What is the problem with this code?

medium

A. The variable 'a' should not be signed for addition.

B. You cannot add signed and unsigned variables directly without casting.

C. The wire 'sum' is declared with wrong bit width.

D. There is no problem; the code is correct.

Solution

1. Step 1: Identify variable types in addition

   Variable 'a' is signed, 'b' is unsigned. Adding signed and unsigned directly can cause unexpected results.

2. Step 2: Understand Verilog rules for mixed signed/unsigned

   Verilog treats unsigned as signed 0-extended or may cause wrong sign extension. Proper casting is needed.

3. Final Answer:

   You cannot add signed and unsigned variables directly without casting. -> Option B

4. Quick Check:

   Mixing signed and unsigned needs casting [OK]

Hint: Avoid mixing signed and unsigned without explicit casting [OK]

Common Mistakes:

• Ignoring signed/unsigned mismatch
• Assuming bit width is the only issue
• Thinking signed variables can't be added

5. You want to store the result of subtracting two 5-bit unsigned numbers a and b in a signed 6-bit variable diff. Which Verilog code correctly handles the signed result?

hard

A. reg signed [5:0] diff = a - b;

B. reg [5:0] diff = a - b;

C. reg signed [5:0] diff = $signed(a) - $signed(b);

D. reg signed [4:0] diff = a - b;

Solution

1. Step 1: Understand the problem of unsigned subtraction

   Subtracting unsigned numbers can produce negative results, so result must be signed and wide enough.

2. Step 2: Check casting and bit width

   reg signed [5:0] diff = $signed(a) - $signed(b); casts both operands to signed before subtraction and uses 6 bits for result, correctly handling negative values.

3. Final Answer:

   reg signed [5:0] diff = $signed(a) - $signed(b); -> Option C

4. Quick Check:

   Cast operands signed before subtracting unsigned numbers [OK]

Hint: Cast unsigned to signed before subtracting to get correct sign [OK]

Common Mistakes:

• Not casting operands to signed
• Using too few bits for result
• Assuming unsigned subtraction can yield negative