Signed vs unsigned representation in Verilog - Quick Revision & Key Differences

Recall & Review

beginner

What is the difference between signed and unsigned numbers in Verilog?

Signed numbers can represent both positive and negative values, while unsigned numbers represent only non-negative values (zero and positive).

beginner

How do you declare a signed variable in Verilog?

Use the keyword signed before the variable type, for example: reg signed [7:0] my_var;

intermediate

What happens if you perform arithmetic operations between signed and unsigned variables in Verilog?

Verilog treats the signed operand as unsigned when performing arithmetic with an unsigned operand, which can lead to unexpected results. It's best to explicitly cast or use matching types.

intermediate

Why is it important to know if a number is signed or unsigned in hardware design?

Because signed and unsigned numbers are stored and interpreted differently in hardware, affecting arithmetic results, overflow behavior, and logic design.

beginner

How does Verilog represent negative numbers in signed variables?

Verilog uses two's complement representation for signed numbers, where the most significant bit indicates the sign (0 for positive, 1 for negative).

In Verilog, which keyword is used to declare a signed variable?

A reg

B signed

C int

D unsigned

The keyword signed is used to declare signed variables in Verilog.

What does the most significant bit (MSB) represent in a signed Verilog number?

A The sign of the number

B The magnitude of the number

C Always zero

D The parity bit

In signed numbers, the MSB indicates the sign: 0 for positive, 1 for negative.

If you add a signed and an unsigned number in Verilog without casting, what might happen?

A The unsigned number is ignored

B The operation is not allowed

C Unexpected results due to type mismatch

D The signed number is converted to unsigned

Mixing signed and unsigned without explicit casting can cause unexpected results.

Which number range can an 8-bit unsigned variable represent?

A 0 to 255

B -128 to 127

C -255 to 255

D 0 to 127

An 8-bit unsigned variable represents values from 0 to 2^8 - 1, which is 0 to 255.

How are negative numbers stored in signed Verilog variables?

A Sign-magnitude

B Floating point

C One's complement

D Two's complement

Verilog uses two's complement to represent negative signed numbers.

Explain how signed and unsigned numbers differ in Verilog and why this matters in hardware design.

Think about how the sign bit changes the number range and calculations.

Describe how to declare signed and unsigned variables in Verilog and what happens if you mix them in operations.

Focus on declaration syntax and arithmetic behavior.

Practice

1. Which of the following statements about signed and unsigned variables in Verilog is correct?

easy

A. Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers.

B. Unsigned variables can hold negative numbers, signed variables cannot.

C. Signed and unsigned variables behave the same in all calculations.

D. You declare unsigned variables using the signed keyword.

Solution

1. Step 1: Understand signed vs unsigned meaning

   Signed variables can represent negative and positive values, unsigned only positive values.

2. Step 2: Check declaration keywords

   Signed variables use the signed keyword; unsigned variables do not use it.

3. Final Answer:

   Signed variables can hold both negative and positive numbers, unsigned variables hold only positive numbers. -> Option A

4. Quick Check:

   Signed = negative and positive [OK]

Hint: Signed means negative and positive; unsigned means only positive [OK]

Common Mistakes:

• Thinking unsigned can hold negative numbers
• Confusing declaration keywords
• Assuming signed and unsigned behave identically

2. Which is the correct way to declare a 8-bit signed variable in Verilog?

easy

A. reg [7:0] my_var;

B. reg signed my_var [7:0];

C. reg unsigned [7:0] my_var;

D. reg signed [7:0] my_var;

Solution

1. Step 1: Recall syntax for signed declaration

   In Verilog, signed variables are declared with the keyword signed before the bit range.

2. Step 2: Check each option's syntax

   reg signed [7:0] my_var; uses reg signed [7:0] my_var; which is correct syntax for an 8-bit signed variable.

3. Final Answer:

   reg signed [7:0] my_var; -> Option D

4. Quick Check:

   Signed keyword before bit range = correct [OK]

Hint: Use 'reg signed [bits]' to declare signed variables [OK]

Common Mistakes:

• Placing 'signed' after variable name
• Using 'unsigned' keyword which is invalid
• Omitting 'signed' keyword for signed variables

3. What is the decimal value of the 4-bit signed number 4'b1101 in Verilog?

medium

A. -3

B. 13

C. -11

D. 3

Solution

1. Step 1: Interpret 4-bit signed binary 1101

   In 4-bit signed, the leftmost bit is sign bit. 1 means negative. The value is two's complement.

2. Step 2: Calculate two's complement value

   Invert bits: 0010, add 1: 0011 (decimal 3). So original number is -3.

3. Final Answer:

   -3 -> Option A

4. Quick Check:

   4-bit signed 1101 = -3 [OK]

Hint: For signed, if MSB=1, find two's complement negative value [OK]

Common Mistakes:

• Reading binary as unsigned
• Ignoring two's complement for negative numbers
• Confusing bit order

4. Given the code snippet:

reg signed [3:0] a = 4'b1010;
reg [3:0] b = 4'b0101;
wire [4:0] sum = a + b;

What is the problem with this code?

medium

A. The variable 'a' should not be signed for addition.

B. You cannot add signed and unsigned variables directly without casting.

C. The wire 'sum' is declared with wrong bit width.

D. There is no problem; the code is correct.

Solution

1. Step 1: Identify variable types in addition

   Variable 'a' is signed, 'b' is unsigned. Adding signed and unsigned directly can cause unexpected results.

2. Step 2: Understand Verilog rules for mixed signed/unsigned

   Verilog treats unsigned as signed 0-extended or may cause wrong sign extension. Proper casting is needed.

3. Final Answer:

   You cannot add signed and unsigned variables directly without casting. -> Option B

4. Quick Check:

   Mixing signed and unsigned needs casting [OK]

Hint: Avoid mixing signed and unsigned without explicit casting [OK]

Common Mistakes:

• Ignoring signed/unsigned mismatch
• Assuming bit width is the only issue
• Thinking signed variables can't be added

5. You want to store the result of subtracting two 5-bit unsigned numbers a and b in a signed 6-bit variable diff. Which Verilog code correctly handles the signed result?

hard

A. reg signed [5:0] diff = a - b;

B. reg [5:0] diff = a - b;

C. reg signed [5:0] diff = $signed(a) - $signed(b);

D. reg signed [4:0] diff = a - b;

Solution

1. Step 1: Understand the problem of unsigned subtraction

   Subtracting unsigned numbers can produce negative results, so result must be signed and wide enough.

2. Step 2: Check casting and bit width

   reg signed [5:0] diff = $signed(a) - $signed(b); casts both operands to signed before subtraction and uses 6 bits for result, correctly handling negative values.

3. Final Answer:

   reg signed [5:0] diff = $signed(a) - $signed(b); -> Option C

4. Quick Check:

   Cast operands signed before subtracting unsigned numbers [OK]

Hint: Cast unsigned to signed before subtracting to get correct sign [OK]

Common Mistakes:

• Not casting operands to signed
• Using too few bits for result
• Assuming unsigned subtraction can yield negative