Decoder design in Verilog - Step-by-Step Execution

Concept Flow - Decoder design

Input bits

↓

Decode input

↓

Activate one output line

↓

All other outputs are 0

↓

End

A decoder takes input bits and activates exactly one output line based on the input value, setting all others to zero.

Execution Sample

Verilog

module decoder2to4(input [1:0] A, output reg [3:0] Y);
  always @(*) begin
    Y = 4'b0000;
    case(A)
      2'b00: Y = 4'b0001;
      2'b01: Y = 4'b0010;
      2'b10: Y = 4'b0100;
      2'b11: Y = 4'b1000;
      default: Y = 4'b0000;
    endcase
  end
endmodule

This 2-to-4 decoder sets one output bit high based on the 2-bit input.

Execution Table

Step	Input A	Action	Output Y
1	00	Set Y=0000; case 00 matched	0001
2	01	Set Y=0000; case 01 matched	0010
3	10	Set Y=0000; case 10 matched	0100
4	11	Set Y=0000; case 11 matched	1000
5	Others	No match (default case)	0000

💡 All input combinations covered; decoder outputs one-hot signal.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	Final
A	00	00	01	10	11	11
Y	0000	0001	0010	0100	1000	1000

Key Moments - 3 Insights

Why do we set Y to 0000 before the case statement?

Setting Y to 0000 first ensures only one output bit is high after the case matches, preventing multiple outputs from being active. See execution_table rows 1-4 where Y resets before assignment.

What happens if input A is outside the defined cases?

In this design, all 2-bit inputs are covered, so no undefined input exists. If an undefined input occurred, Y would remain 0000 as initialized. See execution_table row 5.

Why is only one output bit set to 1 at a time?

Because a decoder activates exactly one output line corresponding to the input value, ensuring a one-hot output. This is shown in each execution_table row where only one bit in Y is 1.

Visual Quiz - 3 Questions

Look at the execution_table, what is the output Y when input A is 10?

A 0010

B 0100

C 1000

D 0001

💡 Hint

Check execution_table row 3 where input A is 10 and output Y is shown.

At which step does the output Y become 0010?

A Step 2

B Step 1

C Step 3

D Step 4

💡 Hint

Look at execution_table row 2 for output Y values.

If we add a default case setting Y=0000, how would the output change for inputs outside 00-11?

A Output Y would keep previous value

B Output Y would be 1111 for undefined inputs

C Output Y would be 0000 for undefined inputs

D Output Y would cause an error

💡 Hint

Default case sets output to zero; see key_moments about undefined inputs.

Concept Snapshot

Decoder design in Verilog:
- Input: n bits
- Output: 2^n bits
- Exactly one output bit is 1 based on input
- Use case statement inside always block
- Initialize output to zero before case
- Outputs are one-hot encoded

Full Transcript

A decoder takes a binary input and activates exactly one output line corresponding to that input. In Verilog, we use an always block with a case statement to check the input and set the output. Before the case, we set the output to zero to ensure only one bit is active. For example, a 2-to-4 decoder has 2 input bits and 4 output bits. When input is 00, output is 0001; for 01, output is 0010; for 10, output is 0100; and for 11, output is 1000. This one-hot output helps select exactly one line. If input is outside defined cases, output remains zero. This design is simple and common in digital circuits.

Practice

1. What is the main function of a decoder in Verilog?

easy

A. Add two binary numbers

B. Convert binary inputs into one-hot outputs

C. Store data temporarily

D. Generate clock signals

Solution

1. Step 1: Understand decoder purpose

   A decoder takes binary inputs and activates exactly one output line corresponding to the input value.

2. Step 2: Compare options

   Only Convert binary inputs into one-hot outputs describes converting binary inputs into one-hot outputs, which matches the decoder function.

3. Final Answer:

   Convert binary inputs into one-hot outputs -> Option B

4. Quick Check:

   Decoder = binary to one-hot [OK]

Hint: Remember: decoder activates one output per input [OK]

Common Mistakes:

• Confusing decoder with adder
• Thinking decoder stores data
• Mixing decoder with clock generator

2. Which of the following is the correct syntax to start a 2-to-4 decoder module in Verilog?

easy

A. module decoder2to4(input [1:0] in, output reg [3:0] out);

B. module decoder2to4(output [1:0] in, input [3:0] out);

C. module decoder2to4(input in[1:0], output out[3:0]);

D. module decoder2to4(input [3:0] in, output [1:0] out);

Solution

1. Step 1: Check input and output declaration

   Inputs and outputs must be declared with direction and bit width inside square brackets before the variable name.

2. Step 2: Validate syntax correctness

   module decoder2to4(input [1:0] in, output reg [3:0] out); correctly declares input as 2 bits and output as 4 bits with proper syntax.

3. Final Answer:

   module decoder2to4(input [1:0] in, output reg [3:0] out); -> Option A

4. Quick Check:

   Correct module header syntax = module decoder2to4(input [1:0] in, output reg [3:0] out); [OK]

Hint: Inputs before outputs, use [msb:lsb] notation [OK]

Common Mistakes:

• Swapping input and output directions
• Placing bit width after variable name
• Using wrong bit widths

3. Given this Verilog code snippet for a 2-to-4 decoder:

always @(*) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
    default: out = 4'b0000;
  endcase
end

What is the value of out when in = 2'b10?

medium

A. 4'b0100

B. 4'b0010

C. 4'b0001

D. 4'b1000

Solution

1. Step 1: Locate matching case for input

   Input 2'b10 matches the third case line: 2'b10: out = 4'b0100;

2. Step 2: Determine output value

   Output is assigned 4'b0100 for input 2'b10.

3. Final Answer:

   4'b0100 -> Option A

4. Quick Check:

   Input 2'b10 maps to 4'b0100 [OK]

Hint: Match input bits to case labels exactly [OK]

Common Mistakes:

• Confusing binary values
• Ignoring default case
• Misreading bit order

4. Identify the error in this 3-to-8 decoder Verilog code snippet:

always @(*) begin
  case(in)
    3'b000: out = 8'b00000001;
    3'b001: out = 8'b00000010;
    3'b010: out = 8'b00000100;
    3'b011: out = 8'b00001000;
    3'b100: out = 8'b00010000;
    3'b101: out = 8'b00100000;
    3'b110: out = 8'b01000000;
    // Missing case for 3'b111
  endcase
end

medium

A. Case statement syntax is invalid

B. Output width is incorrect

C. Input width should be 4 bits

D. Missing default case to cover all inputs

Solution

1. Step 1: Check case coverage

   The case statement covers inputs 3'b000 to 3'b110 but misses 3'b111.

2. Step 2: Importance of default case

   Without a default case, input 3'b111 leads to undefined output, which is an error.

3. Final Answer:

   Missing default case to cover all inputs -> Option D

4. Quick Check:

   Always include default case in decoders [OK]

Hint: Always add default case for full input coverage [OK]

Common Mistakes:

• Forgetting default case
• Assuming all inputs covered without default
• Incorrect input or output widths

5. You want to design a 4-to-16 decoder in Verilog using a case statement. Which approach correctly handles all inputs and ensures only one output bit is high at a time?

hard

A. Use if-else statements checking each bit of input separately to assign outputs

B. Use a case statement with only 8 cases and assign outputs for the rest as zeros

C. Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros

D. Use a for loop inside always block to assign outputs based on input value

Solution

1. Step 1: Understand decoder requirements

   A 4-to-16 decoder must cover all 16 input combinations with one-hot outputs.

2. Step 2: Evaluate options for completeness and correctness

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros uses a case statement with all 16 input cases plus a default, ensuring exactly one output bit is high per input.

3. Final Answer:

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros -> Option C

4. Quick Check:

   Complete case coverage with one-hot outputs = Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros [OK]

Hint: Cover all inputs explicitly with one-hot outputs [OK]

Common Mistakes:

• Missing cases causing undefined outputs
• Using incomplete case statements
• Trying to assign outputs with if-else inefficiently