Decoder design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this 2-to-4 decoder?

Given the following Verilog code for a 2-to-4 decoder, what will be the output y when a = 2'b10?

Verilog

module decoder2to4(input [1:0] a, output reg [3:0] y);
  always @(*) begin
    y = 4'b0000;
    case(a)
      2'b00: y = 4'b0001;
      2'b01: y = 4'b0010;
      2'b10: y = 4'b0100;
      2'b11: y = 4'b1000;
      default: y = 4'b0000;
    endcase
  end
endmodule

A 4'b0010

B 4'b1000

C 4'b0100

D 4'b0001

💡 Hint

Look at the case statement and match the input a to the output y.

The decoder sets only one bit high corresponding to the binary input. For input 2'b10, the output is 4'b0100.

❓ Predict Output

intermediate

Output of 3-to-8 decoder with enable low

Consider this 3-to-8 decoder with an active-high enable signal. What is the output y when en = 0 and a = 3'b101?

Verilog

module decoder3to8(input [2:0] a, input en, output reg [7:0] y);
  always @(*) begin
    if (en) begin
      y = 8'b00000000;
      y[a] = 1'b1;
    end else begin
      y = 8'b00000000;
    end
  end
endmodule

A 8'b10000000

B 8'b00100000

C 8'b00000100

D 8'b00000000

💡 Hint

Check what happens when enable is low.

When enable is 0, the output is forced to all zeros regardless of input.

🔧 Debug

advanced

Identify the error in this 4-to-16 decoder code

This Verilog code is intended to implement a 4-to-16 decoder. What error will occur when compiling or simulating this code?

Verilog

module decoder4to16(input [3:0] a, output reg [15:0] y);
  always @(*) begin
    y = 16'b0;
    case(a)
      4'b0000: y[0] = 1'b1;
      4'b0001: y[1] = 1'b1;
      4'b0010: y[2] = 1'b1;
      // Missing other cases
    endcase
  end
endmodule

A Synthesis warning: incomplete case statement

B Runtime error: index out of range

C Syntax error: missing semicolon after y = 16'b0

D No error; code works correctly

💡 Hint

Look at the case statement coverage.

The case statement does not cover all possible 4-bit inputs, causing a synthesis warning about incomplete cases.

📝 Syntax

advanced

Which option causes a syntax error in this decoder code?

Which of the following Verilog code snippets for a 2-to-4 decoder will cause a syntax error?

A always @(*) begin y = 4'b0000 if (a == 2'b00) y = 4'b0001; end

B always @(*) begin y = 4'b0000; if (a == 2'b00) y = 4'b0001; else if (a == 2'b01) y = 4'b0010; else if (a == 2'b10) y = 4'b0100; else y = 4'b1000; end

C assign y = (a == 2'b00) ? 4'b0001 : (a == 2'b01) ? 4'b0010 : (a == 2'b10) ? 4'b0100 : 4'b1000;

D always @(*) begin case(a) 2'b00: y = 4'b0001; 2'b01: y = 4'b0010; 2'b10: y = 4'b0100; 2'b11: y = 4'b1000; endcase end

💡 Hint

Check for missing semicolons and proper statement endings.

Option A is missing a semicolon after y = 4'b0000, causing a syntax error.

🚀 Application

expert

How many outputs are high for input 3'b011 in this priority decoder?

This Verilog code implements a 3-to-8 priority decoder. For input a = 3'b011, how many bits in output y will be high (1)?

Verilog

module priority_decoder3to8(input [2:0] a, output reg [7:0] y);
  always @(*) begin
    y = 8'b00000000;
    if (a[2]) y[7] = 1'b1;
    else if (a[1]) y[3] = 1'b1;
    else if (a[0]) y[1] = 1'b1;
  end
endmodule

A 2

B 1

C 3

D 0

💡 Hint

Check which bits of input a are set and which condition triggers first.

For input 3'b011, bit 2 is 0, bit 1 is 1, so only y[3] is set to 1. Only one output bit is high.

Practice

1. What is the main function of a decoder in Verilog?

easy

A. Add two binary numbers

B. Convert binary inputs into one-hot outputs

C. Store data temporarily

D. Generate clock signals

Solution

1. Step 1: Understand decoder purpose

   A decoder takes binary inputs and activates exactly one output line corresponding to the input value.

2. Step 2: Compare options

   Only Convert binary inputs into one-hot outputs describes converting binary inputs into one-hot outputs, which matches the decoder function.

3. Final Answer:

   Convert binary inputs into one-hot outputs -> Option B

4. Quick Check:

   Decoder = binary to one-hot [OK]

Hint: Remember: decoder activates one output per input [OK]

Common Mistakes:

• Confusing decoder with adder
• Thinking decoder stores data
• Mixing decoder with clock generator

2. Which of the following is the correct syntax to start a 2-to-4 decoder module in Verilog?

easy

A. module decoder2to4(input [1:0] in, output reg [3:0] out);

B. module decoder2to4(output [1:0] in, input [3:0] out);

C. module decoder2to4(input in[1:0], output out[3:0]);

D. module decoder2to4(input [3:0] in, output [1:0] out);

Solution

1. Step 1: Check input and output declaration

   Inputs and outputs must be declared with direction and bit width inside square brackets before the variable name.

2. Step 2: Validate syntax correctness

   module decoder2to4(input [1:0] in, output reg [3:0] out); correctly declares input as 2 bits and output as 4 bits with proper syntax.

3. Final Answer:

   module decoder2to4(input [1:0] in, output reg [3:0] out); -> Option A

4. Quick Check:

   Correct module header syntax = module decoder2to4(input [1:0] in, output reg [3:0] out); [OK]

Hint: Inputs before outputs, use [msb:lsb] notation [OK]

Common Mistakes:

• Swapping input and output directions
• Placing bit width after variable name
• Using wrong bit widths

3. Given this Verilog code snippet for a 2-to-4 decoder:

always @(*) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
    default: out = 4'b0000;
  endcase
end

What is the value of out when in = 2'b10?

medium

A. 4'b0100

B. 4'b0010

C. 4'b0001

D. 4'b1000

Solution

1. Step 1: Locate matching case for input

   Input 2'b10 matches the third case line: 2'b10: out = 4'b0100;

2. Step 2: Determine output value

   Output is assigned 4'b0100 for input 2'b10.

3. Final Answer:

   4'b0100 -> Option A

4. Quick Check:

   Input 2'b10 maps to 4'b0100 [OK]

Hint: Match input bits to case labels exactly [OK]

Common Mistakes:

• Confusing binary values
• Ignoring default case
• Misreading bit order

4. Identify the error in this 3-to-8 decoder Verilog code snippet:

always @(*) begin
  case(in)
    3'b000: out = 8'b00000001;
    3'b001: out = 8'b00000010;
    3'b010: out = 8'b00000100;
    3'b011: out = 8'b00001000;
    3'b100: out = 8'b00010000;
    3'b101: out = 8'b00100000;
    3'b110: out = 8'b01000000;
    // Missing case for 3'b111
  endcase
end

medium

A. Case statement syntax is invalid

B. Output width is incorrect

C. Input width should be 4 bits

D. Missing default case to cover all inputs

Solution

1. Step 1: Check case coverage

   The case statement covers inputs 3'b000 to 3'b110 but misses 3'b111.

2. Step 2: Importance of default case

   Without a default case, input 3'b111 leads to undefined output, which is an error.

3. Final Answer:

   Missing default case to cover all inputs -> Option D

4. Quick Check:

   Always include default case in decoders [OK]

Hint: Always add default case for full input coverage [OK]

Common Mistakes:

• Forgetting default case
• Assuming all inputs covered without default
• Incorrect input or output widths

5. You want to design a 4-to-16 decoder in Verilog using a case statement. Which approach correctly handles all inputs and ensures only one output bit is high at a time?

hard

A. Use if-else statements checking each bit of input separately to assign outputs

B. Use a case statement with only 8 cases and assign outputs for the rest as zeros

C. Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros

D. Use a for loop inside always block to assign outputs based on input value

Solution

1. Step 1: Understand decoder requirements

   A 4-to-16 decoder must cover all 16 input combinations with one-hot outputs.

2. Step 2: Evaluate options for completeness and correctness

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros uses a case statement with all 16 input cases plus a default, ensuring exactly one output bit is high per input.

3. Final Answer:

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros -> Option C

4. Quick Check:

   Complete case coverage with one-hot outputs = Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros [OK]

Hint: Cover all inputs explicitly with one-hot outputs [OK]

Common Mistakes:

• Missing cases causing undefined outputs
• Using incomplete case statements
• Trying to assign outputs with if-else inefficiently