Decoder design in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 2-to-4 decoder module with inputs and outputs.

Verilog

module decoder2to4([1]);
  input [1:0] in;
  output reg [3:0] out;
endmodule

Drag options to blanks, or click blank then click option'

Adecoder2to4(in, out)

Bdecoder2to4(input in, output out)

Cdecoder2to4(input [1:0] in, output [3:0] out)

Ddecoder2to4(input in, output reg out)

Attempts:

3 left

💡 Hint

Common Mistakes

Including port types inside the module declaration parentheses.

Using 'reg' keyword in the module port list.

The module declaration requires the module name followed by the port list in parentheses. Option A correctly declares the module with ports in and out.

2fill in blank

medium

Complete the always block sensitivity list to trigger on input changes.

Verilog

always @([1]) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
  endcase
end

Drag options to blanks, or click blank then click option'

Ain

Bin or out

Cposedge in

D*

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'posedge' which is for clocked logic.

Including output signals in sensitivity list unnecessarily.

The sensitivity list * means the always block triggers on any change of signals used inside, which is suitable for combinational logic like a decoder.

3fill in blank

hard

Fix the error in the output assignment inside the always block.

Verilog

always @(*) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = [1];
  endcase
end

Drag options to blanks, or click blank then click option'

A4'b100

B4'b10000

C4'b1000

D4'b000

Attempts:

3 left

💡 Hint

Common Mistakes

Using 5-bit or 3-bit values causing width mismatch.

Assigning all zeros which disables output.

The output for input 2'b11 should be 4'b1000 to set the fourth output bit high. Option C correctly sets this 4-bit value.

4fill in blank

hard

Fill both blanks to complete a 3-to-8 decoder output assignment with enable signal.

Verilog

always @(*) begin
  if (enable == [1]) begin
    out = 8'b[2];
  end else begin
    out = 8'b00000000;
  end
end

Drag options to blanks, or click blank then click option'

A1

B00000001

C00000010

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using enable == 0 which disables output.

Assigning wrong output bit pattern.

The decoder output is active when enable is 1, so the condition is enable == 1. The output for input 0 is 8'b00000001 to set the first bit.

5fill in blank

hard

Fill all three blanks to complete a parameterized decoder module header and output declaration.

Verilog

module decoder#(parameter N = [1])(input [N-1:0] in, output reg [[2]:0] out);
  always @(*) begin
    out = 1 << [3];
  end
endmodule

Drag options to blanks, or click blank then click option'

A3

B7

Cin

D4

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong parameter value for N.

Incorrect output bit range.

Shifting by a constant instead of input.

The parameter N is set to 3 for a 3-bit input. The output width is 2^N - 1 = 7 (bits 7 down to 0). The shift amount is the input in to activate the correct output bit.

Practice

1. What is the main function of a decoder in Verilog?

easy

A. Add two binary numbers

B. Convert binary inputs into one-hot outputs

C. Store data temporarily

D. Generate clock signals

Solution

1. Step 1: Understand decoder purpose

   A decoder takes binary inputs and activates exactly one output line corresponding to the input value.

2. Step 2: Compare options

   Only Convert binary inputs into one-hot outputs describes converting binary inputs into one-hot outputs, which matches the decoder function.

3. Final Answer:

   Convert binary inputs into one-hot outputs -> Option B

4. Quick Check:

   Decoder = binary to one-hot [OK]

Hint: Remember: decoder activates one output per input [OK]

Common Mistakes:

• Confusing decoder with adder
• Thinking decoder stores data
• Mixing decoder with clock generator

2. Which of the following is the correct syntax to start a 2-to-4 decoder module in Verilog?

easy

A. module decoder2to4(input [1:0] in, output reg [3:0] out);

B. module decoder2to4(output [1:0] in, input [3:0] out);

C. module decoder2to4(input in[1:0], output out[3:0]);

D. module decoder2to4(input [3:0] in, output [1:0] out);

Solution

1. Step 1: Check input and output declaration

   Inputs and outputs must be declared with direction and bit width inside square brackets before the variable name.

2. Step 2: Validate syntax correctness

   module decoder2to4(input [1:0] in, output reg [3:0] out); correctly declares input as 2 bits and output as 4 bits with proper syntax.

3. Final Answer:

   module decoder2to4(input [1:0] in, output reg [3:0] out); -> Option A

4. Quick Check:

   Correct module header syntax = module decoder2to4(input [1:0] in, output reg [3:0] out); [OK]

Hint: Inputs before outputs, use [msb:lsb] notation [OK]

Common Mistakes:

• Swapping input and output directions
• Placing bit width after variable name
• Using wrong bit widths

3. Given this Verilog code snippet for a 2-to-4 decoder:

always @(*) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
    default: out = 4'b0000;
  endcase
end

What is the value of out when in = 2'b10?

medium

A. 4'b0100

B. 4'b0010

C. 4'b0001

D. 4'b1000

Solution

1. Step 1: Locate matching case for input

   Input 2'b10 matches the third case line: 2'b10: out = 4'b0100;

2. Step 2: Determine output value

   Output is assigned 4'b0100 for input 2'b10.

3. Final Answer:

   4'b0100 -> Option A

4. Quick Check:

   Input 2'b10 maps to 4'b0100 [OK]

Hint: Match input bits to case labels exactly [OK]

Common Mistakes:

• Confusing binary values
• Ignoring default case
• Misreading bit order

4. Identify the error in this 3-to-8 decoder Verilog code snippet:

always @(*) begin
  case(in)
    3'b000: out = 8'b00000001;
    3'b001: out = 8'b00000010;
    3'b010: out = 8'b00000100;
    3'b011: out = 8'b00001000;
    3'b100: out = 8'b00010000;
    3'b101: out = 8'b00100000;
    3'b110: out = 8'b01000000;
    // Missing case for 3'b111
  endcase
end

medium

A. Case statement syntax is invalid

B. Output width is incorrect

C. Input width should be 4 bits

D. Missing default case to cover all inputs

Solution

1. Step 1: Check case coverage

   The case statement covers inputs 3'b000 to 3'b110 but misses 3'b111.

2. Step 2: Importance of default case

   Without a default case, input 3'b111 leads to undefined output, which is an error.

3. Final Answer:

   Missing default case to cover all inputs -> Option D

4. Quick Check:

   Always include default case in decoders [OK]

Hint: Always add default case for full input coverage [OK]

Common Mistakes:

• Forgetting default case
• Assuming all inputs covered without default
• Incorrect input or output widths

5. You want to design a 4-to-16 decoder in Verilog using a case statement. Which approach correctly handles all inputs and ensures only one output bit is high at a time?

hard

A. Use if-else statements checking each bit of input separately to assign outputs

B. Use a case statement with only 8 cases and assign outputs for the rest as zeros

C. Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros

D. Use a for loop inside always block to assign outputs based on input value

Solution

1. Step 1: Understand decoder requirements

   A 4-to-16 decoder must cover all 16 input combinations with one-hot outputs.

2. Step 2: Evaluate options for completeness and correctness

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros uses a case statement with all 16 input cases plus a default, ensuring exactly one output bit is high per input.

3. Final Answer:

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros -> Option C

4. Quick Check:

   Complete case coverage with one-hot outputs = Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros [OK]

Hint: Cover all inputs explicitly with one-hot outputs [OK]

Common Mistakes:

• Missing cases causing undefined outputs
• Using incomplete case statements
• Trying to assign outputs with if-else inefficiently