Decoder design in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a decoder in digital logic?

A decoder is a circuit that converts binary input signals into a one-hot output, activating only one output line corresponding to the input value.

beginner

How many outputs does a 3-to-8 decoder have?

A 3-to-8 decoder has 8 outputs, one for each possible 3-bit input combination (2^3 = 8).

intermediate

What is the role of enable input in a decoder?

The enable input controls whether the decoder is active. When enable is low, all outputs are inactive (usually zero). When enable is high, the decoder outputs respond to the input.

intermediate

Write a simple Verilog code snippet for a 2-to-4 decoder.

module decoder2to4(input [1:0] in, input en, output reg [3:0] out); always @(*) begin if (en) begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; default: out = 4'b0000; endcase end else begin out = 4'b0000; end end endmodule

beginner

Why is a decoder useful in digital systems?

Decoders are useful for selecting one output line out of many based on input signals, such as in memory address decoding, data routing, and control signal generation.

How many outputs does a 4-to-16 decoder have?

A 12

B 4

C 8

D 16

A 4-to-16 decoder has 16 outputs because 2^4 = 16.

What happens to the outputs of a decoder when the enable input is low?

A Outputs toggle randomly

B Outputs follow the input

C All outputs are zero

D Outputs are all one

When enable is low, the decoder outputs are inactive, usually all zero.

In Verilog, which construct is commonly used to implement a decoder's output logic?

A always @(*) with case statement

B initial block

C for loop

D assign statement only

The always @(*) block with a case statement is commonly used to describe combinational logic like decoders.

What is the output of a 2-to-4 decoder when input is 2'b10 and enable is high?

A 4'b0010

B 4'b0100

C 4'b1000

D 4'b0001

Input 2'b10 corresponds to the third output line, so output is 4'b0100.

Which of the following is NOT a typical use of a decoder?

A Data multiplexing

B Control signal generation

C Memory address decoding

D Data routing

Data multiplexing is done by multiplexers, not decoders.

Explain how a decoder works and describe its main components.

Think about how input bits select one output line.

Write a simple Verilog module for a 3-to-8 decoder with an enable input.

Use a case statement inside an always @(*) block to assign outputs.

Practice

1. What is the main function of a decoder in Verilog?

easy

A. Add two binary numbers

B. Convert binary inputs into one-hot outputs

C. Store data temporarily

D. Generate clock signals

Solution

1. Step 1: Understand decoder purpose

   A decoder takes binary inputs and activates exactly one output line corresponding to the input value.

2. Step 2: Compare options

   Only Convert binary inputs into one-hot outputs describes converting binary inputs into one-hot outputs, which matches the decoder function.

3. Final Answer:

   Convert binary inputs into one-hot outputs -> Option B

4. Quick Check:

   Decoder = binary to one-hot [OK]

Hint: Remember: decoder activates one output per input [OK]

Common Mistakes:

• Confusing decoder with adder
• Thinking decoder stores data
• Mixing decoder with clock generator

2. Which of the following is the correct syntax to start a 2-to-4 decoder module in Verilog?

easy

A. module decoder2to4(input [1:0] in, output reg [3:0] out);

B. module decoder2to4(output [1:0] in, input [3:0] out);

C. module decoder2to4(input in[1:0], output out[3:0]);

D. module decoder2to4(input [3:0] in, output [1:0] out);

Solution

1. Step 1: Check input and output declaration

   Inputs and outputs must be declared with direction and bit width inside square brackets before the variable name.

2. Step 2: Validate syntax correctness

   module decoder2to4(input [1:0] in, output reg [3:0] out); correctly declares input as 2 bits and output as 4 bits with proper syntax.

3. Final Answer:

   module decoder2to4(input [1:0] in, output reg [3:0] out); -> Option A

4. Quick Check:

   Correct module header syntax = module decoder2to4(input [1:0] in, output reg [3:0] out); [OK]

Hint: Inputs before outputs, use [msb:lsb] notation [OK]

Common Mistakes:

• Swapping input and output directions
• Placing bit width after variable name
• Using wrong bit widths

3. Given this Verilog code snippet for a 2-to-4 decoder:

always @(*) begin
  case(in)
    2'b00: out = 4'b0001;
    2'b01: out = 4'b0010;
    2'b10: out = 4'b0100;
    2'b11: out = 4'b1000;
    default: out = 4'b0000;
  endcase
end

What is the value of out when in = 2'b10?

medium

A. 4'b0100

B. 4'b0010

C. 4'b0001

D. 4'b1000

Solution

1. Step 1: Locate matching case for input

   Input 2'b10 matches the third case line: 2'b10: out = 4'b0100;

2. Step 2: Determine output value

   Output is assigned 4'b0100 for input 2'b10.

3. Final Answer:

   4'b0100 -> Option A

4. Quick Check:

   Input 2'b10 maps to 4'b0100 [OK]

Hint: Match input bits to case labels exactly [OK]

Common Mistakes:

• Confusing binary values
• Ignoring default case
• Misreading bit order

4. Identify the error in this 3-to-8 decoder Verilog code snippet:

always @(*) begin
  case(in)
    3'b000: out = 8'b00000001;
    3'b001: out = 8'b00000010;
    3'b010: out = 8'b00000100;
    3'b011: out = 8'b00001000;
    3'b100: out = 8'b00010000;
    3'b101: out = 8'b00100000;
    3'b110: out = 8'b01000000;
    // Missing case for 3'b111
  endcase
end

medium

A. Case statement syntax is invalid

B. Output width is incorrect

C. Input width should be 4 bits

D. Missing default case to cover all inputs

Solution

1. Step 1: Check case coverage

   The case statement covers inputs 3'b000 to 3'b110 but misses 3'b111.

2. Step 2: Importance of default case

   Without a default case, input 3'b111 leads to undefined output, which is an error.

3. Final Answer:

   Missing default case to cover all inputs -> Option D

4. Quick Check:

   Always include default case in decoders [OK]

Hint: Always add default case for full input coverage [OK]

Common Mistakes:

• Forgetting default case
• Assuming all inputs covered without default
• Incorrect input or output widths

5. You want to design a 4-to-16 decoder in Verilog using a case statement. Which approach correctly handles all inputs and ensures only one output bit is high at a time?

hard

A. Use if-else statements checking each bit of input separately to assign outputs

B. Use a case statement with only 8 cases and assign outputs for the rest as zeros

C. Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros

D. Use a for loop inside always block to assign outputs based on input value

Solution

1. Step 1: Understand decoder requirements

   A 4-to-16 decoder must cover all 16 input combinations with one-hot outputs.

2. Step 2: Evaluate options for completeness and correctness

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros uses a case statement with all 16 input cases plus a default, ensuring exactly one output bit is high per input.

3. Final Answer:

   Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros -> Option C

4. Quick Check:

   Complete case coverage with one-hot outputs = Use a case statement with 16 cases for inputs 4'b0000 to 4'b1111, assigning one-hot outputs, plus a default output of all zeros [OK]

Hint: Cover all inputs explicitly with one-hot outputs [OK]

Common Mistakes:

• Missing cases causing undefined outputs
• Using incomplete case statements
• Trying to assign outputs with if-else inefficiently