Conditional (ternary) operator in Verilog - Step-by-Step Execution

Concept Flow - Conditional (ternary) operator

Evaluate condition

Yes↓

Use true expression

↓

Result

No↓

Use false expression

↓

Result

The ternary operator checks a condition; if true, it returns the first value, else the second.

Execution Sample

Verilog

assign out = (sel) ? a : b;

Assigns 'out' to 'a' if 'sel' is true, otherwise to 'b'.

Execution Table

Step	Condition (sel)	True Expression (a)	False Expression (b)	Result (out)
1	0	5	10	10
2	1	5	10	5
3	0	3	7	7
4	1	8	2	8
Exit	-	-	-	End of evaluation

💡 No more inputs; evaluation ends.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	Final
sel	undefined	0	1	0	1	1
a	undefined	5	5	3	8	8
b	undefined	10	10	7	2	2
out	undefined	10	5	7	8	8

Key Moments - 2 Insights

Why does 'out' get the value of 'b' when 'sel' is 0?

Because the condition 'sel' is false (0), the ternary operator chooses the false expression 'b' as shown in execution_table row 1.

What happens if 'sel' is 1?

When 'sel' is true (1), the ternary operator picks the true expression 'a', as seen in execution_table rows 2 and 4.

Visual Quiz - 3 Questions

Look at the execution table, what is 'out' when 'sel' is 0 and 'a' is 5, 'b' is 10?

A 0

B 5

C 10

D 15

💡 Hint

Check execution_table row 1 where sel=0, out=10.

At which step does 'out' become 8?

A Step 1

B Step 4

C Step 2

D Step 3

💡 Hint

Look at execution_table row 4 where out=8.

If 'sel' was always 1, what would 'out' be at step 3?

A 3

B 7

C 8

D 10

💡 Hint

When sel=1, out equals 'a' value; see variable_tracker for 'a' at step 3.

Concept Snapshot

Syntax: condition ? true_expr : false_expr;
Evaluates condition; if true, returns true_expr else false_expr.
Used for simple if-else in one line.
In Verilog, commonly used in assign statements.
Result depends on condition value at runtime.

Full Transcript

The conditional (ternary) operator in Verilog evaluates a condition. If the condition is true (1), it returns the first expression; if false (0), it returns the second. For example, 'assign out = (sel) ? a : b;' means if 'sel' is 1, 'out' gets 'a'; if 'sel' is 0, 'out' gets 'b'. The execution table shows step-by-step how 'out' changes based on 'sel', 'a', and 'b'. This operator is a compact way to write simple if-else logic in hardware description.

Practice

1. What does the conditional (ternary) operator condition ? value_if_true : value_if_false do in Verilog?

easy

A. It repeats a block of code multiple times.

B. It selects one of two values based on the condition's truth.

C. It declares a new variable.

D. It comments out a line of code.

Solution

1. Step 1: Understand the operator's purpose

   The conditional operator evaluates a condition and chooses between two values.

2. Step 2: Recognize the syntax meaning

   If the condition is true, it returns the first value; otherwise, it returns the second value.

3. Final Answer:

   It selects one of two values based on the condition's truth. -> Option B

4. Quick Check:

   Conditional operator chooses value based on condition [OK]

Hint: Remember: condition ? true_value : false_value picks one value [OK]

Common Mistakes:

• Thinking it repeats code like a loop
• Confusing it with variable declaration
• Assuming it comments code

2. Which of the following is the correct syntax for using the conditional (ternary) operator in Verilog?

easy

A. assign out = ? a : b;

B. assign out = a > b ? a, b;

C. assign out = a > b ? a : ;

D. assign out = (a > b) ? a : b;

Solution

1. Step 1: Check the syntax format

   The correct syntax is: condition ? value_if_true : value_if_false;

2. Step 2: Verify each option

   assign out = (a > b) ? a : b; matches the correct syntax with parentheses and colon separating values.

3. Final Answer:

   assign out = (a > b) ? a : b; -> Option D

4. Quick Check:

   Correct ternary syntax uses ? and : properly [OK]

Hint: Look for ? and : with condition before ? [OK]

Common Mistakes:

• Using comma instead of colon
• Missing value after colon
• Starting with ? without condition

3. What is the output value of out after this Verilog code runs?

wire [3:0] a = 4'd7;
wire [3:0] b = 4'd10;
wire [3:0] out;
assign out = (a > b) ? a : b;

medium

A. 10

B. 7

C. 0

D. Syntax error

Solution

1. Step 1: Evaluate the condition (a > b)

   a is 7, b is 10, so 7 > 10 is false.

2. Step 2: Choose value based on condition

   Since condition is false, out gets value b, which is 10.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   7 > 10 is false, so out = b = 10 [OK]

Hint: Check condition result true or false to pick value [OK]

Common Mistakes:

• Assuming a is greater than b
• Confusing true and false branches
• Thinking code has syntax error

4. Identify the error in this Verilog code using the conditional operator:

assign result = (x == 1) ? 5 : ;

medium

A. Condition should use single equals (=)

B. Incorrect use of parentheses

C. Missing value after colon (:)

D. No error, code is correct

Solution

1. Step 1: Check the ternary operator structure

   The operator needs a value after the colon to use if condition is false.

2. Step 2: Identify missing part

   Here, after colon (:), no value is given, causing syntax error.

3. Final Answer:

   Missing value after colon (:) -> Option C

4. Quick Check:

   Conditional operator needs both true and false values [OK]

Hint: Always provide both true and false values after ? and : [OK]

Common Mistakes:

• Leaving false value empty
• Using == incorrectly (it's correct here)
• Ignoring missing value error

5. Given this Verilog snippet, what is the value of final_out?

wire [3:0] a = 4'd3;
wire [3:0] b = 4'd7;
wire [3:0] c = 4'd5;
wire [3:0] final_out;
assign final_out = (a > b) ? ((b > c) ? b : c) : ((a > c) ? a : c);

hard

A. 5

B. 7

C. 3

D. Syntax error

Solution

1. Step 1: Evaluate outer condition (a > b)

   a=3, b=7, so 3 > 7 is false, go to false branch.

2. Step 2: Evaluate inner condition in false branch (a > c)

   a=3, c=5, so 3 > 5 is false, select c which is 5.

3. Final Answer:

   5 -> Option A

4. Quick Check:

   Nested ternary picks c=5 as final_out [OK]

Hint: Evaluate nested conditions step-by-step from outside in [OK]

Common Mistakes:

• Mixing true and false branches
• Ignoring nested ternary structure
• Assuming syntax error without checking