Conditional (ternary) operator in Verilog - Mini Project: Build & Apply

Using the Conditional (ternary) Operator in Verilog

📖 Scenario: You are designing a simple digital circuit that decides the output signal based on an input signal and a threshold.

🎯 Goal: Build a Verilog module that uses the conditional (ternary) operator to assign an output value depending on an input signal.

📋 What You'll Learn

Create a 4-bit input signal called input_signal with a fixed value

Create a 4-bit threshold value called threshold

Use the conditional (ternary) operator to assign a 1-bit output signal called output_signal

Print the value of output_signal in the simulation

💡 Why This Matters

🌍 Real World

Conditional operators are used in digital circuits to make decisions quickly, like turning signals on or off based on sensor inputs.

💼 Career

Understanding conditional operators in Verilog is important for hardware engineers designing efficient and compact digital logic.

1

Create the input signal

Create a 4-bit register called input_signal and set it to 4'b1010.

Verilog

// Declare a 4-bit register called input_signal and set it to 4'b1010
// Your code here

Hint

Use reg [3:0] input_signal = 4'b1010; to declare and set the input signal.

2

Create the threshold value

Inside the module, create a 4-bit register called threshold and set it to 4'b0111.

Verilog

module conditional_operator_example();
  reg [3:0] input_signal = 4'b1010;
  // Declare a 4-bit register called threshold and set it to 4'b0111
  // Your code here
endmodule

Hint

Use reg [3:0] threshold = 4'b0111; to declare and set the threshold.

3

Use the conditional (ternary) operator

Create a 1-bit wire called output_signal and assign it using the conditional (ternary) operator: if input_signal is greater than threshold, set output_signal to 1, else set it to 0.

Verilog

module conditional_operator_example();
  reg [3:0] input_signal = 4'b1010;
  reg [3:0] threshold = 4'b0111;
  // Declare a 1-bit wire called output_signal and assign it using the conditional operator
  // Your code here
endmodule

Hint

Use wire output_signal = (input_signal > threshold) ? 1'b1 : 1'b0; to assign the output signal.

4

Display the output signal

Add an initial block that prints the value of output_signal using $display.

Verilog

module conditional_operator_example();
  reg [3:0] input_signal = 4'b1010;
  reg [3:0] threshold = 4'b0111;
  wire output_signal = (input_signal > threshold) ? 1'b1 : 1'b0;

  // Add an initial block to print output_signal
  // Your code here
endmodule

Hint

Use initial begin $display("Output signal: %b", output_signal); end to print the output.

Practice

1. What does the conditional (ternary) operator condition ? value_if_true : value_if_false do in Verilog?

easy

A. It repeats a block of code multiple times.

B. It selects one of two values based on the condition's truth.

C. It declares a new variable.

D. It comments out a line of code.

Solution

1. Step 1: Understand the operator's purpose

   The conditional operator evaluates a condition and chooses between two values.

2. Step 2: Recognize the syntax meaning

   If the condition is true, it returns the first value; otherwise, it returns the second value.

3. Final Answer:

   It selects one of two values based on the condition's truth. -> Option B

4. Quick Check:

   Conditional operator chooses value based on condition [OK]

Hint: Remember: condition ? true_value : false_value picks one value [OK]

Common Mistakes:

• Thinking it repeats code like a loop
• Confusing it with variable declaration
• Assuming it comments code

2. Which of the following is the correct syntax for using the conditional (ternary) operator in Verilog?

easy

A. assign out = ? a : b;

B. assign out = a > b ? a, b;

C. assign out = a > b ? a : ;

D. assign out = (a > b) ? a : b;

Solution

1. Step 1: Check the syntax format

   The correct syntax is: condition ? value_if_true : value_if_false;

2. Step 2: Verify each option

   assign out = (a > b) ? a : b; matches the correct syntax with parentheses and colon separating values.

3. Final Answer:

   assign out = (a > b) ? a : b; -> Option D

4. Quick Check:

   Correct ternary syntax uses ? and : properly [OK]

Hint: Look for ? and : with condition before ? [OK]

Common Mistakes:

• Using comma instead of colon
• Missing value after colon
• Starting with ? without condition

3. What is the output value of out after this Verilog code runs?

wire [3:0] a = 4'd7;
wire [3:0] b = 4'd10;
wire [3:0] out;
assign out = (a > b) ? a : b;

medium

A. 10

B. 7

C. 0

D. Syntax error

Solution

1. Step 1: Evaluate the condition (a > b)

   a is 7, b is 10, so 7 > 10 is false.

2. Step 2: Choose value based on condition

   Since condition is false, out gets value b, which is 10.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   7 > 10 is false, so out = b = 10 [OK]

Hint: Check condition result true or false to pick value [OK]

Common Mistakes:

• Assuming a is greater than b
• Confusing true and false branches
• Thinking code has syntax error

4. Identify the error in this Verilog code using the conditional operator:

assign result = (x == 1) ? 5 : ;

medium

A. Condition should use single equals (=)

B. Incorrect use of parentheses

C. Missing value after colon (:)

D. No error, code is correct

Solution

1. Step 1: Check the ternary operator structure

   The operator needs a value after the colon to use if condition is false.

2. Step 2: Identify missing part

   Here, after colon (:), no value is given, causing syntax error.

3. Final Answer:

   Missing value after colon (:) -> Option C

4. Quick Check:

   Conditional operator needs both true and false values [OK]

Hint: Always provide both true and false values after ? and : [OK]

Common Mistakes:

• Leaving false value empty
• Using == incorrectly (it's correct here)
• Ignoring missing value error

5. Given this Verilog snippet, what is the value of final_out?

wire [3:0] a = 4'd3;
wire [3:0] b = 4'd7;
wire [3:0] c = 4'd5;
wire [3:0] final_out;
assign final_out = (a > b) ? ((b > c) ? b : c) : ((a > c) ? a : c);

hard

A. 5

B. 7

C. 3

D. Syntax error

Solution

1. Step 1: Evaluate outer condition (a > b)

   a=3, b=7, so 3 > 7 is false, go to false branch.

2. Step 2: Evaluate inner condition in false branch (a > c)

   a=3, c=5, so 3 > 5 is false, select c which is 5.

3. Final Answer:

   5 -> Option A

4. Quick Check:

   Nested ternary picks c=5 as final_out [OK]

Hint: Evaluate nested conditions step-by-step from outside in [OK]

Common Mistakes:

• Mixing true and false branches
• Ignoring nested ternary structure
• Assuming syntax error without checking