Conditional (ternary) operator in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to assign 'out' to 'a' if 'sel' is 1, else 'b'.

Verilog

assign out = sel ? [1] : b;

Drag options to blanks, or click blank then click option'

Asel

Bb

Ca

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping the true and false values.

Using '=' instead of '? :'.

Using '==' instead of '?'.

The conditional operator syntax is condition ? true_value : false_value. Here, if sel is 1, out gets a.

2fill in blank

medium

Complete the code to assign 'result' to 8-bit zero if 'enable' is 0, else to 'data'.

Verilog

assign result = enable ? [1] : 8'b0;

Drag options to blanks, or click blank then click option'

Adata

B8'b1

Cenable

D8'bz

Attempts:

3 left

💡 Hint

Common Mistakes

Using a constant instead of the variable.

Confusing enable with data.

Using wrong bit width constants.

If enable is 1, result should be assigned data. Otherwise, it is zero.

3fill in blank

hard

Fix the error in the conditional assignment to 'flag'.

Verilog

assign flag = (count > 10) ? [1] 1'b1 : 1'b0;

Drag options to blanks, or click blank then click option'

A?

B:

C;

Attempts:

3 left

💡 Hint

Common Mistakes

Using two '?' operators.

Missing the ':' operator.

Using ';' inside the expression.

The conditional operator uses one '?' and one ':'. The code mistakenly has two '?'. The second '?' should be ':'.

4fill in blank

hard

Fill both blanks to assign 'out' to 'x' if 'sel' is 1, else 'y'.

Verilog

assign out = [1] ? [2] : y;

Drag options to blanks, or click blank then click option'

Asel

Bx

Cy

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping true and false values.

Using wrong variable names.

Omitting the condition.

The condition is sel. If true, assign x, else y.

5fill in blank

hard

Fill all three blanks to assign 'out' to uppercase 'ch' if 'enable' is 1 and 'ch' is a lowercase letter, else 'ch'.

Verilog

assign out = (enable && (ch >= [1]) && (ch <= [2])) ? [3] : ch;

Drag options to blanks, or click blank then click option'

A'a'

B'z'

Cch - 32

Dch + 32

Attempts:

3 left

💡 Hint

Common Mistakes

Using uppercase letters in range check.

Adding 32 instead of subtracting.

Wrong character constants.

This checks if ch is between 'a' and 'z' (lowercase letters). If true and enable is 1, it converts ch to uppercase by subtracting 32 (assuming ASCII).

Practice

1. What does the conditional (ternary) operator condition ? value_if_true : value_if_false do in Verilog?

easy

A. It repeats a block of code multiple times.

B. It selects one of two values based on the condition's truth.

C. It declares a new variable.

D. It comments out a line of code.

Solution

1. Step 1: Understand the operator's purpose

   The conditional operator evaluates a condition and chooses between two values.

2. Step 2: Recognize the syntax meaning

   If the condition is true, it returns the first value; otherwise, it returns the second value.

3. Final Answer:

   It selects one of two values based on the condition's truth. -> Option B

4. Quick Check:

   Conditional operator chooses value based on condition [OK]

Hint: Remember: condition ? true_value : false_value picks one value [OK]

Common Mistakes:

• Thinking it repeats code like a loop
• Confusing it with variable declaration
• Assuming it comments code

2. Which of the following is the correct syntax for using the conditional (ternary) operator in Verilog?

easy

A. assign out = ? a : b;

B. assign out = a > b ? a, b;

C. assign out = a > b ? a : ;

D. assign out = (a > b) ? a : b;

Solution

1. Step 1: Check the syntax format

   The correct syntax is: condition ? value_if_true : value_if_false;

2. Step 2: Verify each option

   assign out = (a > b) ? a : b; matches the correct syntax with parentheses and colon separating values.

3. Final Answer:

   assign out = (a > b) ? a : b; -> Option D

4. Quick Check:

   Correct ternary syntax uses ? and : properly [OK]

Hint: Look for ? and : with condition before ? [OK]

Common Mistakes:

• Using comma instead of colon
• Missing value after colon
• Starting with ? without condition

3. What is the output value of out after this Verilog code runs?

wire [3:0] a = 4'd7;
wire [3:0] b = 4'd10;
wire [3:0] out;
assign out = (a > b) ? a : b;

medium

A. 10

B. 7

C. 0

D. Syntax error

Solution

1. Step 1: Evaluate the condition (a > b)

   a is 7, b is 10, so 7 > 10 is false.

2. Step 2: Choose value based on condition

   Since condition is false, out gets value b, which is 10.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   7 > 10 is false, so out = b = 10 [OK]

Hint: Check condition result true or false to pick value [OK]

Common Mistakes:

• Assuming a is greater than b
• Confusing true and false branches
• Thinking code has syntax error

4. Identify the error in this Verilog code using the conditional operator:

assign result = (x == 1) ? 5 : ;

medium

A. Condition should use single equals (=)

B. Incorrect use of parentheses

C. Missing value after colon (:)

D. No error, code is correct

Solution

1. Step 1: Check the ternary operator structure

   The operator needs a value after the colon to use if condition is false.

2. Step 2: Identify missing part

   Here, after colon (:), no value is given, causing syntax error.

3. Final Answer:

   Missing value after colon (:) -> Option C

4. Quick Check:

   Conditional operator needs both true and false values [OK]

Hint: Always provide both true and false values after ? and : [OK]

Common Mistakes:

• Leaving false value empty
• Using == incorrectly (it's correct here)
• Ignoring missing value error

5. Given this Verilog snippet, what is the value of final_out?

wire [3:0] a = 4'd3;
wire [3:0] b = 4'd7;
wire [3:0] c = 4'd5;
wire [3:0] final_out;
assign final_out = (a > b) ? ((b > c) ? b : c) : ((a > c) ? a : c);

hard

A. 5

B. 7

C. 3

D. Syntax error

Solution

1. Step 1: Evaluate outer condition (a > b)

   a=3, b=7, so 3 > 7 is false, go to false branch.

2. Step 2: Evaluate inner condition in false branch (a > c)

   a=3, c=5, so 3 > 5 is false, select c which is 5.

3. Final Answer:

   5 -> Option A

4. Quick Check:

   Nested ternary picks c=5 as final_out [OK]

Hint: Evaluate nested conditions step-by-step from outside in [OK]

Common Mistakes:

• Mixing true and false branches
• Ignoring nested ternary structure
• Assuming syntax error without checking