Conditional (ternary) operator in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of simple ternary operator

What is the output value of result after this Verilog code runs?

Verilog

module test;
  reg [3:0] a = 4'd7;
  reg [3:0] b = 4'd10;
  wire [3:0] result;

  assign result = (a > b) ? a : b;
endmodule

A result = 7

B result = 10

C result = 0

D result = 17

💡 Hint

Check which value is greater between a and b.

The ternary operator checks if a > b. Since 7 is not greater than 10, it returns b which is 10.

❓ Predict Output

intermediate

Nested ternary operator output

What is the value of out after this code executes?

Verilog

module test;
  reg [3:0] x = 4'd5;
  wire [3:0] out;

  assign out = (x < 3) ? 4'd1 : (x < 7) ? 4'd2 : 4'd3;
endmodule

A out = 2

B out = 1

C out = 3

D out = 5

💡 Hint

Evaluate conditions from left to right.

x=5 is not less than 3, so first condition is false. Then check if x < 7, which is true, so out = 2.

🔧 Debug

advanced

Identify the error in ternary operator usage

What error does this Verilog code produce?

Verilog

module test;
  reg [3:0] a = 4'd2;
  reg [3:0] b = 4'd3;
  wire [3:0] result;

  assign result = a > b ? a : b : 4'd0;
endmodule

A No error, result = 3

B TypeError: Mismatched types in ternary

C SyntaxError: Unexpected ':'

D RuntimeError: Invalid assignment

💡 Hint

Check the number of ':' in the ternary expression.

The ternary operator syntax is condition ? true_expr : false_expr. Here there are two ':' which is invalid syntax.

🧠 Conceptual

advanced

Understanding ternary operator precedence

Given the expression a ? b : c ? d : e in Verilog, how is it evaluated?

A Equivalent to <code>a ? b : (c ? d : e)</code>

B Equivalent to <code>(a ? b : c) ? d : e</code>

C Syntax error due to ambiguity

D Evaluates all conditions simultaneously

💡 Hint

Ternary operators associate from right to left.

Ternary operators in Verilog associate right to left, so the expression is parsed as a ? b : (c ? d : e).

🚀 Application

expert

Using ternary operator for conditional bit assignment

What is the value of out after this code runs?

Verilog

module test;
  reg [1:0] sel = 2'b10;
  wire [3:0] out;

  assign out = (sel == 2'b00) ? 4'd1 :
               (sel == 2'b01) ? 4'd2 :
               (sel == 2'b10) ? 4'd4 : 4'd8;
endmodule

A out = 1

B out = 2

C out = 8

D out = 4

💡 Hint

Match sel value with conditions in order.

sel is 2'b10, so the third condition is true, assigning out = 4.

Practice

1. What does the conditional (ternary) operator condition ? value_if_true : value_if_false do in Verilog?

easy

A. It repeats a block of code multiple times.

B. It selects one of two values based on the condition's truth.

C. It declares a new variable.

D. It comments out a line of code.

Solution

1. Step 1: Understand the operator's purpose

   The conditional operator evaluates a condition and chooses between two values.

2. Step 2: Recognize the syntax meaning

   If the condition is true, it returns the first value; otherwise, it returns the second value.

3. Final Answer:

   It selects one of two values based on the condition's truth. -> Option B

4. Quick Check:

   Conditional operator chooses value based on condition [OK]

Hint: Remember: condition ? true_value : false_value picks one value [OK]

Common Mistakes:

• Thinking it repeats code like a loop
• Confusing it with variable declaration
• Assuming it comments code

2. Which of the following is the correct syntax for using the conditional (ternary) operator in Verilog?

easy

A. assign out = ? a : b;

B. assign out = a > b ? a, b;

C. assign out = a > b ? a : ;

D. assign out = (a > b) ? a : b;

Solution

1. Step 1: Check the syntax format

   The correct syntax is: condition ? value_if_true : value_if_false;

2. Step 2: Verify each option

   assign out = (a > b) ? a : b; matches the correct syntax with parentheses and colon separating values.

3. Final Answer:

   assign out = (a > b) ? a : b; -> Option D

4. Quick Check:

   Correct ternary syntax uses ? and : properly [OK]

Hint: Look for ? and : with condition before ? [OK]

Common Mistakes:

• Using comma instead of colon
• Missing value after colon
• Starting with ? without condition

3. What is the output value of out after this Verilog code runs?

wire [3:0] a = 4'd7;
wire [3:0] b = 4'd10;
wire [3:0] out;
assign out = (a > b) ? a : b;

medium

A. 10

B. 7

C. 0

D. Syntax error

Solution

1. Step 1: Evaluate the condition (a > b)

   a is 7, b is 10, so 7 > 10 is false.

2. Step 2: Choose value based on condition

   Since condition is false, out gets value b, which is 10.

3. Final Answer:

   10 -> Option A

4. Quick Check:

   7 > 10 is false, so out = b = 10 [OK]

Hint: Check condition result true or false to pick value [OK]

Common Mistakes:

• Assuming a is greater than b
• Confusing true and false branches
• Thinking code has syntax error

4. Identify the error in this Verilog code using the conditional operator:

assign result = (x == 1) ? 5 : ;

medium

A. Condition should use single equals (=)

B. Incorrect use of parentheses

C. Missing value after colon (:)

D. No error, code is correct

Solution

1. Step 1: Check the ternary operator structure

   The operator needs a value after the colon to use if condition is false.

2. Step 2: Identify missing part

   Here, after colon (:), no value is given, causing syntax error.

3. Final Answer:

   Missing value after colon (:) -> Option C

4. Quick Check:

   Conditional operator needs both true and false values [OK]

Hint: Always provide both true and false values after ? and : [OK]

Common Mistakes:

• Leaving false value empty
• Using == incorrectly (it's correct here)
• Ignoring missing value error

5. Given this Verilog snippet, what is the value of final_out?

wire [3:0] a = 4'd3;
wire [3:0] b = 4'd7;
wire [3:0] c = 4'd5;
wire [3:0] final_out;
assign final_out = (a > b) ? ((b > c) ? b : c) : ((a > c) ? a : c);

hard

A. 5

B. 7

C. 3

D. Syntax error

Solution

1. Step 1: Evaluate outer condition (a > b)

   a=3, b=7, so 3 > 7 is false, go to false branch.

2. Step 2: Evaluate inner condition in false branch (a > c)

   a=3, c=5, so 3 > 5 is false, select c which is 5.

3. Final Answer:

   5 -> Option A

4. Quick Check:

   Nested ternary picks c=5 as final_out [OK]

Hint: Evaluate nested conditions step-by-step from outside in [OK]

Common Mistakes:

• Mixing true and false branches
• Ignoring nested ternary structure
• Assuming syntax error without checking