Concatenation and replication in Verilog - Step-by-Step Execution

Concept Flow - Concatenation and replication

Start

↓

Evaluate Replication

↓

Evaluate Concatenation

↓

Combine Bits

↓

Assign Result

↓

End

The flow shows how Verilog first replicates bits if needed, then concatenates multiple parts, combines them, and assigns the result.

Execution Sample

Verilog

wire [7:0] a, b;
wire [11:0] c;
assign a = 4'b1010;
assign b = {2{a[3:0]}};
assign c = {a, 4'b1100};

This code replicates the 4-bit slice of 'a' twice to form 'b', then concatenates 'a' with 4'b1100 to form 'c'.

Execution Table

Step	Expression	Operation	Intermediate Result	Final Result
1	a = 4'b1010	Assign 4-bit value	1010	a = 00001010 (8 bits)
2	a[3:0]	Slice lower 4 bits	1010	1010
3	{2{a[3:0]}}	Replicate slice twice	1010 1010	b = 10101010 (8 bits)
4	{a, 4'b1100}	Concatenate a and 4'b1100	00001010 1100	c = 000010101100 (12 bits)
5	End	All assignments done	-	-

💡 All concatenation and replication operations complete, variables assigned.

Variable Tracker

Variable	Start	After Step 1	After Step 3	After Step 4	Final
a	undefined	00001010	00001010	00001010	00001010
b	undefined	undefined	10101010	10101010	10101010
c	undefined	undefined	undefined	000010101100	000010101100

Key Moments - 2 Insights

Why does 'b' have 8 bits when we replicate a 4-bit slice twice?

Because replication {2{a[3:0]}} repeats the 4-bit slice two times, making 4 bits * 2 = 8 bits total, as shown in execution_table row 3.

How does concatenation affect the bit width of 'c'?

Concatenation joins 'a' (8 bits) and 4'b1100 (4 bits) to form a 12-bit value, as seen in execution_table row 4.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of 'b' after step 3?

A 10101010

B 00001010

C 1100

D 1010

💡 Hint

Check the 'Intermediate Result' and 'Final Result' columns in row 3.

At which step does the concatenation happen to form 'c'?

A Step 2

B Step 3

C Step 4

D Step 1

💡 Hint

Look for the row where '{a, 4'b1100}' is evaluated in the 'Expression' column.

If we change replication from {2{a[3:0]}} to {3{a[3:0]}}, what will be the bit width of the replication expression {3{a[3:0]}}?

A 8 bits

B 12 bits

C 4 bits

D 16 bits

💡 Hint

Each replication adds 4 bits; 3 times 4 bits equals 12 bits.

Concept Snapshot

Concatenation: Use {a, b} to join bits side-by-side.
Replication: Use {N{bits}} to repeat bits N times.
Bit width grows by sum of parts in concatenation.
Replication multiplies bit width by N.
Common in wiring and signal construction in Verilog.

Full Transcript

This visual execution shows how Verilog handles concatenation and replication. First, a 4-bit value is assigned to 'a'. Then, the lower 4 bits of 'a' are replicated twice to form 'b', doubling the bit width from 4 to 8 bits. Next, 'a' is concatenated with a 4-bit constant to form 'c', increasing the bit width to 12 bits. The variable tracker shows how each variable changes after each step. Key moments clarify why replication multiplies bit width and how concatenation adds widths. The quiz tests understanding of these steps and bit widths.

Practice

1. What does the Verilog expression {4{1'b0}} produce?

easy

A. A 4-bit vector with all bits set to 0

B. A 1-bit vector with value 4

C. A syntax error due to incorrect replication

D. A 4-bit vector with all bits set to 1

Solution

1. Step 1: Understand replication syntax

   The expression {4{1'b0}} means repeat the bit 0 four times.

2. Step 2: Construct the resulting vector

   Repeating 1'b0 four times creates a 4-bit vector: 0000.

3. Final Answer:

   A 4-bit vector with all bits set to 0 -> Option A

4. Quick Check:

   Replication repeats bits = 0000 [OK]

Hint: Replication repeats bits exactly as many times as the number [OK]

Common Mistakes:

• Confusing replication with concatenation
• Thinking it produces a single bit with value equal to the number
• Assuming it creates all ones instead of zeros

2. Which of the following is the correct syntax to concatenate a 3-bit vector a and a 2-bit vector b in Verilog?

easy

A. [a, b]

B. (a + b)

C. {a, b}

D. {a + b}

Solution

1. Step 1: Recall concatenation syntax

   Concatenation in Verilog uses curly braces with commas between signals.

2. Step 2: Identify correct syntax

   The correct way to join vectors a and b side by side is {a, b}.

3. Final Answer:

   {a, b} -> Option C

4. Quick Check:

   Concatenation uses braces and commas = {a, b} [OK]

Hint: Use curly braces with commas for concatenation [OK]

Common Mistakes:

• Using parentheses instead of braces
• Using plus sign inside braces incorrectly
• Using square brackets which are invalid here

3. What is the 8-bit value of the following Verilog expression?
{2{2'b10}, 4'b0011}

medium

A. 10101011

B. 10100011

C. 10100000

D. 10010011

Solution

1. Step 1: Evaluate the replication part

   2'b10 is 2 bits: 10. Replicated twice: 10 10.

2. Step 2: Concatenate with 4'b0011

   Concatenate 10 10 (4 bits) with 0011 (4 bits) to get 10100011.

3. Final Answer:

   10101011 -> Option A

4. Quick Check:

   Replication + concatenation = 10101011 [OK]

Hint: Replicate first, then concatenate signals [OK]

Common Mistakes:

• Miscounting bits after replication
• Concatenating in wrong order
• Confusing binary digits during replication

4. Identify the error in this Verilog code snippet:

wire [7:0] out;
assign out = {3{2'b11}, 3'b101};

medium

A. Replication count must be a variable, not a constant

B. Concatenation operands have mismatched bit widths causing size mismatch

C. Replication syntax is incorrect, missing parentheses

D. No error, code is correct

Solution

1. Step 1: Calculate bits from replication

   3{2'b11} replicates 2 bits three times = 6 bits total.

2. Step 2: Calculate bits from concatenation

   Concatenating 6 bits with 3 bits (3'b101) gives 9 bits total, but out is 8 bits wide.

3. Step 3: Identify size mismatch error

   The assigned value is 9 bits, but out expects 8 bits, causing a size mismatch error.

4. Final Answer:

   Concatenation operands have mismatched bit widths causing size mismatch -> Option B

5. Quick Check:

   Bit width mismatch in concatenation = error [OK]

Hint: Check total bits match target width in concatenation [OK]

Common Mistakes:

• Ignoring bit width mismatch warnings
• Assuming replication count must be variable
• Thinking replication syntax needs parentheses

5. You want to create a 12-bit signal sig by repeating a 3-bit pattern 3'b101 four times using the replication operator. Which Verilog expression correctly does this?

hard

A. assign sig = {4(3'b101)};

B. assign sig = {3'b101, 3'b101, 3'b101, 3'b101};

C. assign sig = {3'b101 * 4};

D. assign sig = {4{3'b101}};

Solution

1. Step 1: Understand replication for repeating patterns

   Using {4{3'b101}} repeats the 3-bit pattern four times, producing 12 bits.

2. Step 2: Compare with other options

   Manual concatenation assign sig = {3'b101, 3'b101, 3'b101, 3'b101}; repeats explicitly but doesn't use the replication operator; assign sig = {3'b101 * 4}; is invalid syntax; assign sig = {4(3'b101)}; is incorrect syntax.

3. Final Answer:

   assign sig = {4{3'b101}}; -> Option D

4. Quick Check:

   Replication repeats pattern cleanly = assign sig = {4{3'b101}}; [OK]

Hint: Use replication braces {count{pattern}} for repeated signals [OK]

Common Mistakes:

• Using multiplication instead of replication
• Writing replication without braces
• Manually concatenating repeated patterns instead of replicating