Concatenation and replication in Verilog - Mini Project: Build & Apply

Concatenation and replication

📖 Scenario: You are designing a simple digital circuit in Verilog that needs to combine and repeat signals to form a wider bus.

🎯 Goal: Build a Verilog module that demonstrates how to concatenate two 4-bit inputs into an 8-bit output and replicate a 2-bit input four times to form an 8-bit output.

📋 What You'll Learn

Create two 4-bit input signals named a and b

Create one 2-bit input signal named c

Create two 8-bit output signals named concat_out and replicate_out

Use concatenation to combine a and b into concat_out

Use replication to repeat c four times into replicate_out

Print the values of concat_out and replicate_out in an initial block

💡 Why This Matters

🌍 Real World

Concatenation and replication are common in digital design to build wider buses or repeat patterns efficiently.

💼 Career

Understanding these concepts is essential for hardware engineers working with Verilog to design and simulate digital circuits.

1

Create input signals

Create two 4-bit input signals called a and b inside a module named concat_replicate.

Verilog

module concat_replicate();
// Your code here
endmodule

Hint

Use reg [3:0] a; and reg [3:0] b; inside the module.

2

Add input and output signals

Add a 2-bit input signal called c and two 8-bit output signals called concat_out and replicate_out inside the concat_replicate module.

Verilog

module concat_replicate();
  reg [3:0] a;
  reg [3:0] b;
  // Add reg [1:0] c and reg [7:0] concat_out, replicate_out below
  // Your code here
endmodule

Hint

Declare c as reg [1:0] c; and outputs as reg [7:0] concat_out; and reg [7:0] replicate_out;.

3

Concatenate and replicate signals

Inside an initial block, assign concat_out to the concatenation of a and b using {a, b}. Assign replicate_out to the replication of c four times using {4{c}}. Also, initialize a, b, and c with values 4'b1010, 4'b0101, and 2'b11 respectively.

Verilog

module concat_replicate();
  reg [3:0] a;
  reg [3:0] b;
  reg [1:0] c;
  reg [7:0] concat_out;
  reg [7:0] replicate_out;

  initial begin
    // Initialize a, b, c
    // Assign concat_out = {a, b}
    // Assign replicate_out = {4{c}}
    // Your code here
  end
endmodule

Hint

Use {a, b} for concatenation and {4{c}} for replication inside the initial block.

4

Display the results

Add $display statements inside the initial block to print the values of concat_out and replicate_out in binary format.

Verilog

module concat_replicate();
  reg [3:0] a;
  reg [3:0] b;
  reg [1:0] c;
  reg [7:0] concat_out;
  reg [7:0] replicate_out;

  initial begin
    a = 4'b1010;
    b = 4'b0101;
    c = 2'b11;
    concat_out = {a, b};
    replicate_out = {4{c}};
    // Add $display statements to print concat_out and replicate_out
    // Your code here
  end
endmodule

Hint

Use $display("concat_out = %b", concat_out); and $display("replicate_out = %b", replicate_out); inside the initial block.

Practice

1. What does the Verilog expression {4{1'b0}} produce?

easy

A. A 4-bit vector with all bits set to 0

B. A 1-bit vector with value 4

C. A syntax error due to incorrect replication

D. A 4-bit vector with all bits set to 1

Solution

1. Step 1: Understand replication syntax

   The expression {4{1'b0}} means repeat the bit 0 four times.

2. Step 2: Construct the resulting vector

   Repeating 1'b0 four times creates a 4-bit vector: 0000.

3. Final Answer:

   A 4-bit vector with all bits set to 0 -> Option A

4. Quick Check:

   Replication repeats bits = 0000 [OK]

Hint: Replication repeats bits exactly as many times as the number [OK]

Common Mistakes:

• Confusing replication with concatenation
• Thinking it produces a single bit with value equal to the number
• Assuming it creates all ones instead of zeros

2. Which of the following is the correct syntax to concatenate a 3-bit vector a and a 2-bit vector b in Verilog?

easy

A. [a, b]

B. (a + b)

C. {a, b}

D. {a + b}

Solution

1. Step 1: Recall concatenation syntax

   Concatenation in Verilog uses curly braces with commas between signals.

2. Step 2: Identify correct syntax

   The correct way to join vectors a and b side by side is {a, b}.

3. Final Answer:

   {a, b} -> Option C

4. Quick Check:

   Concatenation uses braces and commas = {a, b} [OK]

Hint: Use curly braces with commas for concatenation [OK]

Common Mistakes:

• Using parentheses instead of braces
• Using plus sign inside braces incorrectly
• Using square brackets which are invalid here

3. What is the 8-bit value of the following Verilog expression?
{2{2'b10}, 4'b0011}

medium

A. 10101011

B. 10100011

C. 10100000

D. 10010011

Solution

1. Step 1: Evaluate the replication part

   2'b10 is 2 bits: 10. Replicated twice: 10 10.

2. Step 2: Concatenate with 4'b0011

   Concatenate 10 10 (4 bits) with 0011 (4 bits) to get 10100011.

3. Final Answer:

   10101011 -> Option A

4. Quick Check:

   Replication + concatenation = 10101011 [OK]

Hint: Replicate first, then concatenate signals [OK]

Common Mistakes:

• Miscounting bits after replication
• Concatenating in wrong order
• Confusing binary digits during replication

4. Identify the error in this Verilog code snippet:

wire [7:0] out;
assign out = {3{2'b11}, 3'b101};

medium

A. Replication count must be a variable, not a constant

B. Concatenation operands have mismatched bit widths causing size mismatch

C. Replication syntax is incorrect, missing parentheses

D. No error, code is correct

Solution

1. Step 1: Calculate bits from replication

   3{2'b11} replicates 2 bits three times = 6 bits total.

2. Step 2: Calculate bits from concatenation

   Concatenating 6 bits with 3 bits (3'b101) gives 9 bits total, but out is 8 bits wide.

3. Step 3: Identify size mismatch error

   The assigned value is 9 bits, but out expects 8 bits, causing a size mismatch error.

4. Final Answer:

   Concatenation operands have mismatched bit widths causing size mismatch -> Option B

5. Quick Check:

   Bit width mismatch in concatenation = error [OK]

Hint: Check total bits match target width in concatenation [OK]

Common Mistakes:

• Ignoring bit width mismatch warnings
• Assuming replication count must be variable
• Thinking replication syntax needs parentheses

5. You want to create a 12-bit signal sig by repeating a 3-bit pattern 3'b101 four times using the replication operator. Which Verilog expression correctly does this?

hard

A. assign sig = {4(3'b101)};

B. assign sig = {3'b101, 3'b101, 3'b101, 3'b101};

C. assign sig = {3'b101 * 4};

D. assign sig = {4{3'b101}};

Solution

1. Step 1: Understand replication for repeating patterns

   Using {4{3'b101}} repeats the 3-bit pattern four times, producing 12 bits.

2. Step 2: Compare with other options

   Manual concatenation assign sig = {3'b101, 3'b101, 3'b101, 3'b101}; repeats explicitly but doesn't use the replication operator; assign sig = {3'b101 * 4}; is invalid syntax; assign sig = {4(3'b101)}; is incorrect syntax.

3. Final Answer:

   assign sig = {4{3'b101}}; -> Option D

4. Quick Check:

   Replication repeats pattern cleanly = assign sig = {4{3'b101}}; [OK]

Hint: Use replication braces {count{pattern}} for repeated signals [OK]

Common Mistakes:

• Using multiplication instead of replication
• Writing replication without braces
• Manually concatenating repeated patterns instead of replicating