Concatenation and replication in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of concatenation and replication in Verilog

What is the 8-bit output of the following Verilog code snippet?

wire [7:0] result;
assign result = {2{4'b1010}};

Verilog

wire [7:0] result;
assign result = {2{4'b1010}};

A 8'b11110000

B 8'b10101001

C 8'b10101010

D 8'b01010101

💡 Hint

Replication repeats the 4-bit pattern twice to form 8 bits.

The replication operator {2{4'b1010}} repeats the 4-bit pattern '1010' two times, resulting in '10101010'.

❓ Predict Output

intermediate

Concatenation of different bit widths

What is the 6-bit value of 'out' after this assignment?

wire [5:0] out;
assign out = {3'b101, 3'b011};

Verilog

wire [5:0] out;
assign out = {3'b101, 3'b011};

A 6'b101011

B 6'b000000

C 6'b111000

D 6'b011101

💡 Hint

Concatenation joins bits left to right.

Concatenation {3'b101, 3'b011} joins '101' as the upper 3 bits and '011' as the lower 3 bits, forming 6'b101011.

❓ Predict Output

advanced

Replication with concatenation producing 12 bits

What is the 12-bit value of 'data' after this assignment?

wire [11:0] data;
assign data = {3{4'b1100}};

Verilog

wire [11:0] data;
assign data = {3{4'b1100}};

A 12'b110000110000

B 12'b111100001111

C 12'b001100110011

D 12'b110011001100

💡 Hint

Replication repeats the 4-bit pattern three times.

The replication operator {3{4'b1100}} repeats '1100' three times, resulting in 12'b110011001100.

❓ Predict Output

advanced

Concatenation and replication with mixed widths

What is the 10-bit value of 'signal' after this assignment?

wire [9:0] signal;
assign signal = {2{3'b101}, 4'b1100};

Verilog

wire [9:0] signal;
assign signal = {2{3'b101}, 4'b1100};

A 10'b1011011100

B 10'b1011011001

C 10'b1111001010

D 10'b1100101101

💡 Hint

Replication repeats 3'b101 twice, then concatenates 4'b1100.

Replication {2{3'b101}} produces '101101' (6 bits), concatenated with '1100' (4 bits) results in 10'b1011011100.

🧠 Conceptual

expert

Understanding replication operator behavior

Which statement correctly describes the behavior of the replication operator in Verilog?

A It repeats the bit pattern only if the pattern is a single bit.

B It repeats the bit pattern a specified number of times, concatenating the copies left to right.

C It repeats the bit pattern and inserts zeros between each copy.

D It repeats the bit pattern but reverses each copy before concatenation.

💡 Hint

Think about how {3{4'b1010}} expands.

The replication operator repeats the given bit pattern the specified number of times, concatenating the copies in order from left to right without modification.

Practice

1. What does the Verilog expression {4{1'b0}} produce?

easy

A. A 4-bit vector with all bits set to 0

B. A 1-bit vector with value 4

C. A syntax error due to incorrect replication

D. A 4-bit vector with all bits set to 1

Solution

1. Step 1: Understand replication syntax

   The expression {4{1'b0}} means repeat the bit 0 four times.

2. Step 2: Construct the resulting vector

   Repeating 1'b0 four times creates a 4-bit vector: 0000.

3. Final Answer:

   A 4-bit vector with all bits set to 0 -> Option A

4. Quick Check:

   Replication repeats bits = 0000 [OK]

Hint: Replication repeats bits exactly as many times as the number [OK]

Common Mistakes:

• Confusing replication with concatenation
• Thinking it produces a single bit with value equal to the number
• Assuming it creates all ones instead of zeros

2. Which of the following is the correct syntax to concatenate a 3-bit vector a and a 2-bit vector b in Verilog?

easy

A. [a, b]

B. (a + b)

C. {a, b}

D. {a + b}

Solution

1. Step 1: Recall concatenation syntax

   Concatenation in Verilog uses curly braces with commas between signals.

2. Step 2: Identify correct syntax

   The correct way to join vectors a and b side by side is {a, b}.

3. Final Answer:

   {a, b} -> Option C

4. Quick Check:

   Concatenation uses braces and commas = {a, b} [OK]

Hint: Use curly braces with commas for concatenation [OK]

Common Mistakes:

• Using parentheses instead of braces
• Using plus sign inside braces incorrectly
• Using square brackets which are invalid here

3. What is the 8-bit value of the following Verilog expression?
{2{2'b10}, 4'b0011}

medium

A. 10101011

B. 10100011

C. 10100000

D. 10010011

Solution

1. Step 1: Evaluate the replication part

   2'b10 is 2 bits: 10. Replicated twice: 10 10.

2. Step 2: Concatenate with 4'b0011

   Concatenate 10 10 (4 bits) with 0011 (4 bits) to get 10100011.

3. Final Answer:

   10101011 -> Option A

4. Quick Check:

   Replication + concatenation = 10101011 [OK]

Hint: Replicate first, then concatenate signals [OK]

Common Mistakes:

• Miscounting bits after replication
• Concatenating in wrong order
• Confusing binary digits during replication

4. Identify the error in this Verilog code snippet:

wire [7:0] out;
assign out = {3{2'b11}, 3'b101};

medium

A. Replication count must be a variable, not a constant

B. Concatenation operands have mismatched bit widths causing size mismatch

C. Replication syntax is incorrect, missing parentheses

D. No error, code is correct

Solution

1. Step 1: Calculate bits from replication

   3{2'b11} replicates 2 bits three times = 6 bits total.

2. Step 2: Calculate bits from concatenation

   Concatenating 6 bits with 3 bits (3'b101) gives 9 bits total, but out is 8 bits wide.

3. Step 3: Identify size mismatch error

   The assigned value is 9 bits, but out expects 8 bits, causing a size mismatch error.

4. Final Answer:

   Concatenation operands have mismatched bit widths causing size mismatch -> Option B

5. Quick Check:

   Bit width mismatch in concatenation = error [OK]

Hint: Check total bits match target width in concatenation [OK]

Common Mistakes:

• Ignoring bit width mismatch warnings
• Assuming replication count must be variable
• Thinking replication syntax needs parentheses

5. You want to create a 12-bit signal sig by repeating a 3-bit pattern 3'b101 four times using the replication operator. Which Verilog expression correctly does this?

hard

A. assign sig = {4(3'b101)};

B. assign sig = {3'b101, 3'b101, 3'b101, 3'b101};

C. assign sig = {3'b101 * 4};

D. assign sig = {4{3'b101}};

Solution

1. Step 1: Understand replication for repeating patterns

   Using {4{3'b101}} repeats the 3-bit pattern four times, producing 12 bits.

2. Step 2: Compare with other options

   Manual concatenation assign sig = {3'b101, 3'b101, 3'b101, 3'b101}; repeats explicitly but doesn't use the replication operator; assign sig = {3'b101 * 4}; is invalid syntax; assign sig = {4(3'b101)}; is incorrect syntax.

3. Final Answer:

   assign sig = {4{3'b101}}; -> Option D

4. Quick Check:

   Replication repeats pattern cleanly = assign sig = {4{3'b101}}; [OK]

Hint: Use replication braces {count{pattern}} for repeated signals [OK]

Common Mistakes:

• Using multiplication instead of replication
• Writing replication without braces
• Manually concatenating repeated patterns instead of replicating