Concatenation and replication in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is concatenation in Verilog?

Concatenation in Verilog is a way to join multiple signals or variables together to form a single larger vector. It uses curly braces { } to combine bits or vectors side by side.

beginner

How do you replicate a signal multiple times in Verilog?

Replication in Verilog repeats a signal or vector multiple times using the syntax {N{signal}}, where N is the number of times to repeat the signal.

intermediate

Example: What does {a, b, c} do if a=2'b01, b=2'b10, c=1'b1?

It concatenates the bits to form a 5-bit vector: 2'b01 (a), 2'b10 (b), and 1'b1 (c) become 5'b01101.

intermediate

Example: What is the result of {3{2'b10}}?

It replicates 2'b10 three times to form 6 bits: 6'b101010.

beginner

Why use concatenation and replication in hardware design?

They help build wider buses, initialize vectors, and create repeated patterns easily, making code shorter and clearer.

Which symbol is used for concatenation in Verilog?

A {}

B []

C ()

D <>

Concatenation uses curly braces { } to join signals.

What does {4{1'b0}} produce?

A 1'b1

B 1'b0

C 4'b0000

D 4'b1111

Replication repeats 1'b0 four times to make 4'b0000.

If a=2'b11 and b=1'b0, what is {a,b}?

A 3'b011

B 3'b101

C 3'b100

D 3'b110

Concatenation joins a=11 and b=0 to 110.

How many bits does {2{3'b101}} have?

A 3 bits

B 6 bits

C 2 bits

D 5 bits

Replication doubles the 3-bit vector to 6 bits.

Which is a valid use of replication?

A Creating a bus with repeated patterns

B Adding two numbers

C Declaring a module

D Assigning a single bit

Replication is used to create repeated bit patterns in buses.

Explain how concatenation works in Verilog and give a simple example.

Think about putting pieces side by side to make a bigger piece.

Describe replication in Verilog and why it is useful in hardware design.

Imagine copying the same pattern many times in a row.

Practice

1. What does the Verilog expression {4{1'b0}} produce?

easy

A. A 4-bit vector with all bits set to 0

B. A 1-bit vector with value 4

C. A syntax error due to incorrect replication

D. A 4-bit vector with all bits set to 1

Solution

1. Step 1: Understand replication syntax

   The expression {4{1'b0}} means repeat the bit 0 four times.

2. Step 2: Construct the resulting vector

   Repeating 1'b0 four times creates a 4-bit vector: 0000.

3. Final Answer:

   A 4-bit vector with all bits set to 0 -> Option A

4. Quick Check:

   Replication repeats bits = 0000 [OK]

Hint: Replication repeats bits exactly as many times as the number [OK]

Common Mistakes:

• Confusing replication with concatenation
• Thinking it produces a single bit with value equal to the number
• Assuming it creates all ones instead of zeros

2. Which of the following is the correct syntax to concatenate a 3-bit vector a and a 2-bit vector b in Verilog?

easy

A. [a, b]

B. (a + b)

C. {a, b}

D. {a + b}

Solution

1. Step 1: Recall concatenation syntax

   Concatenation in Verilog uses curly braces with commas between signals.

2. Step 2: Identify correct syntax

   The correct way to join vectors a and b side by side is {a, b}.

3. Final Answer:

   {a, b} -> Option C

4. Quick Check:

   Concatenation uses braces and commas = {a, b} [OK]

Hint: Use curly braces with commas for concatenation [OK]

Common Mistakes:

• Using parentheses instead of braces
• Using plus sign inside braces incorrectly
• Using square brackets which are invalid here

3. What is the 8-bit value of the following Verilog expression?
{2{2'b10}, 4'b0011}

medium

A. 10101011

B. 10100011

C. 10100000

D. 10010011

Solution

1. Step 1: Evaluate the replication part

   2'b10 is 2 bits: 10. Replicated twice: 10 10.

2. Step 2: Concatenate with 4'b0011

   Concatenate 10 10 (4 bits) with 0011 (4 bits) to get 10100011.

3. Final Answer:

   10101011 -> Option A

4. Quick Check:

   Replication + concatenation = 10101011 [OK]

Hint: Replicate first, then concatenate signals [OK]

Common Mistakes:

• Miscounting bits after replication
• Concatenating in wrong order
• Confusing binary digits during replication

4. Identify the error in this Verilog code snippet:

wire [7:0] out;
assign out = {3{2'b11}, 3'b101};

medium

A. Replication count must be a variable, not a constant

B. Concatenation operands have mismatched bit widths causing size mismatch

C. Replication syntax is incorrect, missing parentheses

D. No error, code is correct

Solution

1. Step 1: Calculate bits from replication

   3{2'b11} replicates 2 bits three times = 6 bits total.

2. Step 2: Calculate bits from concatenation

   Concatenating 6 bits with 3 bits (3'b101) gives 9 bits total, but out is 8 bits wide.

3. Step 3: Identify size mismatch error

   The assigned value is 9 bits, but out expects 8 bits, causing a size mismatch error.

4. Final Answer:

   Concatenation operands have mismatched bit widths causing size mismatch -> Option B

5. Quick Check:

   Bit width mismatch in concatenation = error [OK]

Hint: Check total bits match target width in concatenation [OK]

Common Mistakes:

• Ignoring bit width mismatch warnings
• Assuming replication count must be variable
• Thinking replication syntax needs parentheses

5. You want to create a 12-bit signal sig by repeating a 3-bit pattern 3'b101 four times using the replication operator. Which Verilog expression correctly does this?

hard

A. assign sig = {4(3'b101)};

B. assign sig = {3'b101, 3'b101, 3'b101, 3'b101};

C. assign sig = {3'b101 * 4};

D. assign sig = {4{3'b101}};

Solution

1. Step 1: Understand replication for repeating patterns

   Using {4{3'b101}} repeats the 3-bit pattern four times, producing 12 bits.

2. Step 2: Compare with other options

   Manual concatenation assign sig = {3'b101, 3'b101, 3'b101, 3'b101}; repeats explicitly but doesn't use the replication operator; assign sig = {3'b101 * 4}; is invalid syntax; assign sig = {4(3'b101)}; is incorrect syntax.

3. Final Answer:

   assign sig = {4{3'b101}}; -> Option D

4. Quick Check:

   Replication repeats pattern cleanly = assign sig = {4{3'b101}}; [OK]

Hint: Use replication braces {count{pattern}} for repeated signals [OK]

Common Mistakes:

• Using multiplication instead of replication
• Writing replication without braces
• Manually concatenating repeated patterns instead of replicating