Bitwise operators (AND, OR, XOR, NOT) in Verilog - Step-by-Step Execution

Concept Flow - Bitwise operators (AND, OR, XOR, NOT)

Input bits A and B

↓

Apply AND (&) operation

→Result AND

↓

Apply OR (|) operation

→Result OR

↓

Apply XOR (^) operation

→Result XOR

↓

Apply NOT (~) operation on A

→Result NOT A

Bitwise operators take two input bits (or one for NOT) and apply logical operations on each bit position independently.

Execution Sample

Verilog

module bitwise_ops();
  reg [3:0] A = 4'b1100;
  reg [3:0] B = 4'b1010;
  wire [3:0] and_res = A & B;
  wire [3:0] or_res = A | B;
  wire [3:0] xor_res = A ^ B;
  wire [3:0] not_res = ~A;
endmodule

This code applies bitwise AND, OR, XOR between A and B, and bitwise NOT on A.

Execution Table

Step	Operation	Input A	Input B	Bitwise Result	Explanation
1	AND (&)	1100	1010	1000	Each bit ANDed: 1&1=1,1&0=0,0&1=0,0&0=0
2	OR (|)	1100	1010	1110	Each bit ORed: 1|1=1,1|0=1,0|1=1,0|0=0
3	XOR (^)	1100	1010	0110	Each bit XORed: 1^1=0,1^0=1,0^1=1,0^0=0
4	NOT (~) on A	1100	-	0011	Each bit NOTed: ~1=0,~1=0,~0=1,~0=1
5	End	-	-	-	All bitwise operations completed

💡 All bitwise operations on 4-bit inputs completed.

Variable Tracker

Variable	Initial	After Step 1	After Step 2	After Step 3	After Step 4	Final
A	1100	1100	1100	1100	1100	1100
B	1010	1010	1010	1010	1010	1010
and_res	----	1000	1000	1000	1000	1000
or_res	----	----	1110	1110	1110	1110
xor_res	----	----	----	0110	0110	0110
not_res	----	----	----	----	0011	0011

Key Moments - 3 Insights

Why does the NOT operator only take one input instead of two?

The NOT operator (~) flips each bit of a single input independently, so it only needs one operand as shown in step 4 of the execution_table.

Why are the results 4 bits long even though operations are done bit by bit?

Each bitwise operator works on each bit position independently but the output keeps the same bit width as inputs, as seen in all steps of the execution_table.

Why does XOR produce 0 when both bits are 1?

XOR outputs 1 only when bits differ; if both bits are 1, XOR outputs 0, demonstrated in step 3 of the execution_table.

Visual Quiz - 3 Questions

Look at the execution_table, what is the result of the AND operation at step 1?

A 1000

B 1110

C 0110

D 0011

💡 Hint

Check the 'Bitwise Result' column at step 1 in the execution_table.

At which step does the NOT operator apply, and what is its output?

A Step 2, 1110

B Step 3, 0110

C Step 4, 0011

D Step 1, 1000

💡 Hint

Look for the NOT operation in the 'Operation' column and its corresponding result.

If input B changed to 1111, what would be the OR result at step 2?

A 1100

B 1111

C 1010

D 0110

💡 Hint

OR operation outputs 1 if either bit is 1; with B=1111, all bits ORed with A=1100 become 1.

Concept Snapshot

Bitwise operators work on each bit of inputs independently.
AND (&) outputs 1 only if both bits are 1.
OR (|) outputs 1 if at least one bit is 1.
XOR (^) outputs 1 if bits differ.
NOT (~) flips each bit of a single input.
All outputs keep the same bit width as inputs.

Full Transcript

This visual execution trace shows how bitwise operators in Verilog work on 4-bit inputs A and B. Each operator processes bits independently: AND outputs 1 only when both bits are 1, OR outputs 1 if either bit is 1, XOR outputs 1 if bits differ, and NOT flips bits of a single input. The execution_table traces each step with inputs and results, while variable_tracker shows how variables hold values after each operation. Key moments clarify common confusions about single input for NOT, bit width preservation, and XOR behavior. The visual quiz tests understanding by referencing specific steps and results. This helps beginners see exactly how bitwise operations manipulate bits in hardware description language.

Practice

1. Which bitwise operator in Verilog flips each bit of a binary number?
~ is the symbol for which operator?

easy

A. XOR

B. NOT

C. OR

D. AND

Solution

1. Step 1: Understand the operator symbol

   The symbol ~ in Verilog is used to flip bits, meaning it changes 0 to 1 and 1 to 0.

2. Step 2: Match symbol to operator name

   This flipping action corresponds to the NOT operator, which inverts each bit.

3. Final Answer:

   NOT -> Option B

4. Quick Check:

   ~ = NOT [OK]

Hint: Remember ~ flips bits, so it's NOT operator [OK]

Common Mistakes:

• Confusing ~ with AND (&)
• Thinking ~ is OR (|)
• Mixing ~ with XOR (^)

2. Which of the following is the correct Verilog syntax for bitwise AND of two 4-bit vectors a and b?

easy

A. assign c = a & b;

B. assign c = a && b;

C. assign c = a | b;

D. assign c = a ^ b;

Solution

1. Step 1: Identify bitwise AND operator

   In Verilog, the bitwise AND operator is &, which works bit by bit on vectors.

2. Step 2: Check syntax correctness

   The syntax assign c = a & b; correctly assigns the bitwise AND of a and b to c.

3. Final Answer:

   assign c = a & b; -> Option A

4. Quick Check:

   & is bitwise AND [OK]

Hint: Use single & for bitwise AND, not && [OK]

Common Mistakes:

• Using && which is logical AND
• Confusing & with | (OR)
• Using ^ which is XOR

3. What is the 4-bit result of the following Verilog expression?
assign result = 4'b1101 ^ 4'b1011;

medium

A. 4'b1000

B. 4'b1110

C. 4'b0110

D. 4'b0010

Solution

1. Step 1: Understand XOR operation

   XOR (^) compares bits: if bits differ, result is 1; if same, result is 0.

2. Step 2: Calculate bitwise XOR

   Bits: 1101 ^ 1011
   1 ^ 1 = 0
   1 ^ 0 = 1
   0 ^ 1 = 1
   1 ^ 1 = 0
   Result = 0110

3. Final Answer:

   4'b0110 -> Option C

4. Quick Check:

   1101 ^ 1011 = 0110 [OK]

Hint: XOR gives 1 only if bits differ [OK]

Common Mistakes:

• Mixing XOR with OR or AND results
• Calculating bits incorrectly
• Confusing bit order

4. Identify the error in this Verilog code snippet:

assign out = a |& b;

where a and b are 4-bit vectors.

medium

A. Should use logical OR || instead

B. Missing semicolon at the end

C. Vectors a and b must be single bits

D. Operator |& is invalid for bitwise operations

Solution

1. Step 1: Check operator validity

   The operator |& is not a valid bitwise operator in Verilog; it is a reduction operator but used incorrectly here.

2. Step 2: Understand correct bitwise OR usage

   For bitwise OR between vectors, use | alone, like a | b.

3. Final Answer:

   Operator |& is invalid for bitwise operations -> Option D

4. Quick Check:

   |& is invalid here [OK]

Hint: Use single | for bitwise OR, not |& [OK]

Common Mistakes:

• Confusing reduction and bitwise operators
• Forgetting semicolon (though present here)
• Using logical OR || instead of bitwise |

5. Given two 4-bit vectors a = 4'b1010 and b = 4'b1100, which Verilog expression produces a 4-bit vector where bits are set to 1 only if the corresponding bits in a and b differ?

hard

A. assign c = a ^ b;

B. assign c = a & b;

C. assign c = a | b;

D. assign c = ~a;

Solution

1. Step 1: Understand the requirement

   We want bits set to 1 only where a and b differ.

2. Step 2: Identify operator for differing bits

   The XOR operator (^) sets bits to 1 where bits differ and 0 where they are the same.

3. Step 3: Apply XOR to given vectors

   For a = 1010 and b = 1100, a ^ b = 0110, which matches the requirement.

4. Final Answer:

   assign c = a ^ b; -> Option A

5. Quick Check:

   XOR gives 1 for differing bits [OK]

Hint: Use XOR (^) to find differing bits [OK]

Common Mistakes:

• Using AND (&) which gives common bits
• Using OR (|) which sets bits if either is 1
• Using NOT (~) which flips all bits