Bitwise operators (AND, OR, XOR, NOT) in Verilog - Mini Project: Build & Apply

Bitwise Operators (AND, OR, XOR, NOT) in Verilog

📖 Scenario: You are designing a simple digital logic module that processes two 4-bit input signals. You want to apply basic bitwise operations to these inputs to understand how AND, OR, XOR, and NOT work in hardware design.

🎯 Goal: Build a Verilog module that takes two 4-bit inputs and produces outputs for bitwise AND, OR, XOR, and NOT operations.

📋 What You'll Learn

Create two 4-bit input registers with exact values

Create a 4-bit register for NOT operation input

Use bitwise AND, OR, XOR, and NOT operators on the inputs

Display the results using $display statements

💡 Why This Matters

🌍 Real World

Bitwise operations are fundamental in digital circuit design, used in creating logic gates, masks, and control signals.

💼 Career

Understanding bitwise operators is essential for hardware engineers and FPGA developers working with Verilog or VHDL.

1

DATA SETUP: Define two 4-bit input registers

Create two 4-bit registers called a and b with the exact binary values 4'b1100 and 4'b1010 respectively.

Verilog

// Define 4-bit registers a and b with given binary values
// Your code here

Hint

Use reg [3:0] to declare 4-bit registers and assign binary values using 4'bxxxx notation.

2

CONFIGURATION: Define a 4-bit register for NOT operation

Add a 4-bit register called c with the exact binary value 4'b0110 to use for the NOT operation.

Verilog

module bitwise_demo();
  reg [3:0] a = 4'b1100;
  reg [3:0] b = 4'b1010;
  // Define 4-bit register c with given binary value
  // Your code here
endmodule

Hint

Declare c similarly to a and b with the specified binary value.

3

CORE LOGIC: Apply bitwise AND, OR, XOR, and NOT operations

Create 4-bit wires called and_result, or_result, xor_result, and not_result. Use assign statements to assign them the bitwise AND of a and b, OR of a and b, XOR of a and b, and NOT of c respectively.

Verilog

module bitwise_demo();
  reg [3:0] a = 4'b1100;
  reg [3:0] b = 4'b1010;
  reg [3:0] c = 4'b0110;

  // Declare 4-bit wires and assign bitwise operations
  // Your code here

  initial begin
  end
endmodule

Hint

Use assign statements to connect wires to the bitwise operations.

4

OUTPUT: Display the results of bitwise operations

Inside the initial block, add $display statements to print the values of a, b, c, and the results and_result, or_result, xor_result, and not_result in binary format using %b.

Verilog

module bitwise_demo();
  reg [3:0] a = 4'b1100;
  reg [3:0] b = 4'b1010;
  reg [3:0] c = 4'b0110;

  wire [3:0] and_result;
  wire [3:0] or_result;
  wire [3:0] xor_result;
  wire [3:0] not_result;

  assign and_result = a & b;
  assign or_result = a | b;
  assign xor_result = a ^ b;
  assign not_result = ~c;

  initial begin
    // Add $display statements to show all values in binary
    // Your code here
  end
endmodule

Hint

Use $display("label = %b", variable); to print binary values with labels.

Practice

1. Which bitwise operator in Verilog flips each bit of a binary number?
~ is the symbol for which operator?

easy

A. XOR

B. NOT

C. OR

D. AND

Solution

1. Step 1: Understand the operator symbol

   The symbol ~ in Verilog is used to flip bits, meaning it changes 0 to 1 and 1 to 0.

2. Step 2: Match symbol to operator name

   This flipping action corresponds to the NOT operator, which inverts each bit.

3. Final Answer:

   NOT -> Option B

4. Quick Check:

   ~ = NOT [OK]

Hint: Remember ~ flips bits, so it's NOT operator [OK]

Common Mistakes:

• Confusing ~ with AND (&)
• Thinking ~ is OR (|)
• Mixing ~ with XOR (^)

2. Which of the following is the correct Verilog syntax for bitwise AND of two 4-bit vectors a and b?

easy

A. assign c = a & b;

B. assign c = a && b;

C. assign c = a | b;

D. assign c = a ^ b;

Solution

1. Step 1: Identify bitwise AND operator

   In Verilog, the bitwise AND operator is &, which works bit by bit on vectors.

2. Step 2: Check syntax correctness

   The syntax assign c = a & b; correctly assigns the bitwise AND of a and b to c.

3. Final Answer:

   assign c = a & b; -> Option A

4. Quick Check:

   & is bitwise AND [OK]

Hint: Use single & for bitwise AND, not && [OK]

Common Mistakes:

• Using && which is logical AND
• Confusing & with | (OR)
• Using ^ which is XOR

3. What is the 4-bit result of the following Verilog expression?
assign result = 4'b1101 ^ 4'b1011;

medium

A. 4'b1000

B. 4'b1110

C. 4'b0110

D. 4'b0010

Solution

1. Step 1: Understand XOR operation

   XOR (^) compares bits: if bits differ, result is 1; if same, result is 0.

2. Step 2: Calculate bitwise XOR

   Bits: 1101 ^ 1011
   1 ^ 1 = 0
   1 ^ 0 = 1
   0 ^ 1 = 1
   1 ^ 1 = 0
   Result = 0110

3. Final Answer:

   4'b0110 -> Option C

4. Quick Check:

   1101 ^ 1011 = 0110 [OK]

Hint: XOR gives 1 only if bits differ [OK]

Common Mistakes:

• Mixing XOR with OR or AND results
• Calculating bits incorrectly
• Confusing bit order

4. Identify the error in this Verilog code snippet:

assign out = a |& b;

where a and b are 4-bit vectors.

medium

A. Should use logical OR || instead

B. Missing semicolon at the end

C. Vectors a and b must be single bits

D. Operator |& is invalid for bitwise operations

Solution

1. Step 1: Check operator validity

   The operator |& is not a valid bitwise operator in Verilog; it is a reduction operator but used incorrectly here.

2. Step 2: Understand correct bitwise OR usage

   For bitwise OR between vectors, use | alone, like a | b.

3. Final Answer:

   Operator |& is invalid for bitwise operations -> Option D

4. Quick Check:

   |& is invalid here [OK]

Hint: Use single | for bitwise OR, not |& [OK]

Common Mistakes:

• Confusing reduction and bitwise operators
• Forgetting semicolon (though present here)
• Using logical OR || instead of bitwise |

5. Given two 4-bit vectors a = 4'b1010 and b = 4'b1100, which Verilog expression produces a 4-bit vector where bits are set to 1 only if the corresponding bits in a and b differ?

hard

A. assign c = a ^ b;

B. assign c = a & b;

C. assign c = a | b;

D. assign c = ~a;

Solution

1. Step 1: Understand the requirement

   We want bits set to 1 only where a and b differ.

2. Step 2: Identify operator for differing bits

   The XOR operator (^) sets bits to 1 where bits differ and 0 where they are the same.

3. Step 3: Apply XOR to given vectors

   For a = 1010 and b = 1100, a ^ b = 0110, which matches the requirement.

4. Final Answer:

   assign c = a ^ b; -> Option A

5. Quick Check:

   XOR gives 1 for differing bits [OK]

Hint: Use XOR (^) to find differing bits [OK]

Common Mistakes:

• Using AND (&) which gives common bits
• Using OR (|) which sets bits if either is 1
• Using NOT (~) which flips all bits