Why synthesis rules matter in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register.

Verilog

reg [[1]:0] my_reg;

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A3

B4

C7

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 instead of 3 as the upper index causes a 5-bit register.

Forgetting to specify the bit range leads to a 1-bit register.

The register is 4 bits wide, so the index goes from 3 down to 0.

2fill in blank

medium

Complete the code to assign the value of input 'a' to output 'b' using continuous assignment.

Verilog

assign b = [1];

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Ab

Ba

C0

D1'b0

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning 'b' to itself causes a continuous loop.

Assigning a constant like 0 disconnects the input.

The continuous assignment connects output 'b' to input 'a'.

3fill in blank

hard

Fix the error in the always block sensitivity list to correctly trigger on clock's rising edge.

Verilog

always @([1]) begin
  q <= d;
end

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Aclk

Bnegedge clk

Cposedge clk

Dd

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' alone triggers on any change, causing unintended behavior.

Using 'negedge clk' triggers on falling edge, which may not be desired.

The always block should trigger on the positive edge of the clock for synchronous logic.

4fill in blank

hard

Fill both blanks to create a combinational always block that triggers on changes to inputs 'a' or 'b'.

Verilog

always @([1] or [2]) begin
  y = a & b;
end

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Aa

Bb

Cposedge clk

Dnegedge rst

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock edges causes the block to behave like sequential logic.

Omitting inputs from sensitivity list causes simulation mismatches.

The always block triggers whenever 'a' or 'b' changes, making it combinational logic.

5fill in blank

hard

Fill all three blanks to create a synchronous reset flip-flop with active low reset.

Verilog

always @([1] or [2]) begin
  if (![3]) begin
    q <= 0;
  end else begin
    q <= d;
  end
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bnegedge rst_n

Crst_n

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'rst_n' directly in sensitivity list without edge causes incorrect behavior.

Checking 'if (rst_n)' instead of 'if (!rst_n)' reverses reset logic.

The always block triggers on the clock's rising edge and reset's falling edge. The reset signal is active low, so we check if 'rst_n' is low.

Practice

1. Why is it important to follow synthesis rules when writing Verilog code?

easy

A. Because synthesis rules ensure the code can be converted into real hardware

B. Because synthesis rules make the code run faster in simulation

C. Because synthesis rules help the code look cleaner

D. Because synthesis rules allow the code to run on any software

Solution

1. Step 1: Understand synthesis purpose

   Synthesis converts Verilog code into hardware circuits.

2. Step 2: Connect rules to hardware creation

   Following synthesis rules ensures the code can be correctly transformed into hardware.

3. Final Answer:

   Because synthesis rules ensure the code can be converted into real hardware -> Option A

4. Quick Check:

   Synthesis rules = hardware conversion [OK]

Hint: Synthesis rules = code to hardware conversion [OK]

Common Mistakes:

• Confusing synthesis rules with simulation speed
• Thinking synthesis rules only affect code style
• Believing synthesis rules affect software compatibility

2. Which of the following Verilog code snippets follows synthesis rules for combinational logic?

easy

A. always @(posedge clk) begin out = in1 & in2; end

B. always @(negedge clk) begin out <= in1 | in2; end

C. initial begin out = 1'b0; end

D. always @(*) begin out = in1 & in2; end

Solution

1. Step 1: Identify combinational logic sensitivity list

   Combinational logic uses always @(*) to react to input changes.

2. Step 2: Check each option

   always @(*) begin out = in1 & in2; end uses always @(*) with blocking assignment, correct for combinational logic.

3. Final Answer:

   always @(*) begin out = in1 & in2; end -> Option D

4. Quick Check:

   Combinational logic uses always @(*) [OK]

Hint: Combinational logic uses always @(*) blocks [OK]

Common Mistakes:

• Using clock edges for combinational logic
• Using non-blocking assignments in combinational always blocks
• Using initial blocks for synthesis

3. What will be the output of this Verilog code after synthesis if clk is a clock and reset is active high?

module test(input clk, reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

medium

A. q follows d asynchronously ignoring reset

B. q resets to 0 when reset is high, else q follows d on clock edge

C. q never resets and holds previous value

D. q resets to 1 when reset is high

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clk or reset.

2. Step 2: Understand reset behavior

   If reset is high, q is set to 0 immediately (asynchronous reset). Otherwise, q follows d on clock edge.

3. Final Answer:

   q resets to 0 when reset is high, else q follows d on clock edge -> Option B

4. Quick Check:

   Asynchronous reset sets q=0, else q=d [OK]

Hint: Check sensitivity list for async reset behavior [OK]

Common Mistakes:

• Assuming reset is synchronous
• Ignoring reset in output behavior
• Confusing reset value as 1 instead of 0

4. Identify the synthesis error in this Verilog code:

always @(posedge clk) begin
  if (enable)
    count = count + 1;
end

medium

A. Using blocking assignment inside sequential always block

B. Missing sensitivity to reset signal

C. Using non-blocking assignment instead of blocking

D. No error, code is synthesizable

Solution

1. Step 1: Check assignment type in sequential block

   Sequential blocks triggered by clock edges should use non-blocking assignments (<=).

2. Step 2: Identify error in code

   The code uses blocking assignment (=) inside a clocked always block, which can cause incorrect synthesis.

3. Final Answer:

   Using blocking assignment inside sequential always block -> Option A

4. Quick Check:

   Sequential always blocks need non-blocking assignments [OK]

Hint: Use <= in clocked always blocks, not = [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Ignoring reset signals in counters
• Assuming blocking assignments are always okay

5. You want to design a 4-bit counter that resets asynchronously and counts up on each clock edge only when enable is high. Which of the following code snippets follows synthesis rules correctly?

hard

A. always @(posedge clk or posedge reset) begin
if (reset) count = 0;
else if (enable) count <= count + 1;
end

B. always @(posedge clk) begin
if (reset) count = 0;
else if (enable) count = count + 1;
end

C. always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

D. always @(posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

Solution

1. Step 1: Check asynchronous reset sensitivity

   Asynchronous reset requires reset in sensitivity list (posedge reset).

2. Step 2: Verify assignment types and conditions

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end uses non-blocking assignments (<=) and includes reset in sensitivity list, correctly implementing async reset and enable control.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end -> Option C

4. Quick Check:

   Async reset in sensitivity + non-blocking assignments [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Omitting reset from sensitivity list for async reset
• Mixing blocking and non-blocking assignments