Why synthesis rules matter in Verilog - See It in Action

Why synthesis rules matter

📖 Scenario: You are designing a simple digital circuit using Verilog. To make sure your design works correctly on real hardware, you need to follow synthesis rules. These rules help the synthesis tool convert your code into actual logic gates without errors.

🎯 Goal: You will write a Verilog module that counts from 0 to 3 repeatedly. You will follow synthesis rules to create a proper clocked process and output the count value. This will help you understand why synthesis rules matter for hardware design.

📋 What You'll Learn

Create a Verilog module named counter with inputs and outputs

Declare a 2-bit register called count to hold the counter value

Use an always block triggered on the rising edge of clk

Increment count from 0 to 3 and then wrap back to 0

Output the current count value on a 2-bit output out

💡 Why This Matters

🌍 Real World

Digital circuits like timers, clocks, and state machines use counters. Following synthesis rules ensures your design works correctly on real chips.

💼 Career

Hardware engineers and FPGA designers must write synthesizable Verilog code. Understanding synthesis rules is key to creating reliable hardware.

1

Create the module and declare inputs and outputs

Write a Verilog module named counter with an input clk and a 2-bit output out. Declare a 2-bit register called count inside the module.

Verilog

module counter(input clk, output reg [1:0] out);
// Your code here
endmodule

Hint

Remember to declare count as a register because it will hold state.

2

Add the clocked process to update the counter

Inside the counter module, add an always block triggered on the rising edge of clk. This block will update the count register.

Verilog

module counter(input clk, output reg [1:0] out);
    reg [1:0] count;
    always @(posedge clk) begin
        // Your code here
    end
endmodule

Hint

Use always @(posedge clk) to create a clocked process.

3

Implement the counting logic with wrap-around

Inside the always block, write code to increment count by 1 each clock cycle. When count reaches 3, reset it back to 0.

Verilog

module counter(input clk, output reg [1:0] out);
    reg [1:0] count;
    always @(posedge clk) begin
        // Your code here
    end
endmodule

Hint

Use an if statement to check if count is 3 (binary 11) and reset it.

4

Assign the counter value to the output

After updating count, assign its value to the output out inside the always block. Then, write a testbench code to print the out value for 5 clock cycles.

Verilog

module counter(input clk, output reg [1:0] out);
    reg [1:0] count;
    always @(posedge clk) begin
        // Your code here
    end
endmodule

// Testbench code below
// Your code here

Hint

Assign out <= count; inside the always block. Use a testbench with a clock toggling every 5 time units and print out values.

Practice

1. Why is it important to follow synthesis rules when writing Verilog code?

easy

A. Because synthesis rules ensure the code can be converted into real hardware

B. Because synthesis rules make the code run faster in simulation

C. Because synthesis rules help the code look cleaner

D. Because synthesis rules allow the code to run on any software

Solution

1. Step 1: Understand synthesis purpose

   Synthesis converts Verilog code into hardware circuits.

2. Step 2: Connect rules to hardware creation

   Following synthesis rules ensures the code can be correctly transformed into hardware.

3. Final Answer:

   Because synthesis rules ensure the code can be converted into real hardware -> Option A

4. Quick Check:

   Synthesis rules = hardware conversion [OK]

Hint: Synthesis rules = code to hardware conversion [OK]

Common Mistakes:

• Confusing synthesis rules with simulation speed
• Thinking synthesis rules only affect code style
• Believing synthesis rules affect software compatibility

2. Which of the following Verilog code snippets follows synthesis rules for combinational logic?

easy

A. always @(posedge clk) begin out = in1 & in2; end

B. always @(negedge clk) begin out <= in1 | in2; end

C. initial begin out = 1'b0; end

D. always @(*) begin out = in1 & in2; end

Solution

1. Step 1: Identify combinational logic sensitivity list

   Combinational logic uses always @(*) to react to input changes.

2. Step 2: Check each option

   always @(*) begin out = in1 & in2; end uses always @(*) with blocking assignment, correct for combinational logic.

3. Final Answer:

   always @(*) begin out = in1 & in2; end -> Option D

4. Quick Check:

   Combinational logic uses always @(*) [OK]

Hint: Combinational logic uses always @(*) blocks [OK]

Common Mistakes:

• Using clock edges for combinational logic
• Using non-blocking assignments in combinational always blocks
• Using initial blocks for synthesis

3. What will be the output of this Verilog code after synthesis if clk is a clock and reset is active high?

module test(input clk, reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

medium

A. q follows d asynchronously ignoring reset

B. q resets to 0 when reset is high, else q follows d on clock edge

C. q never resets and holds previous value

D. q resets to 1 when reset is high

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clk or reset.

2. Step 2: Understand reset behavior

   If reset is high, q is set to 0 immediately (asynchronous reset). Otherwise, q follows d on clock edge.

3. Final Answer:

   q resets to 0 when reset is high, else q follows d on clock edge -> Option B

4. Quick Check:

   Asynchronous reset sets q=0, else q=d [OK]

Hint: Check sensitivity list for async reset behavior [OK]

Common Mistakes:

• Assuming reset is synchronous
• Ignoring reset in output behavior
• Confusing reset value as 1 instead of 0

4. Identify the synthesis error in this Verilog code:

always @(posedge clk) begin
  if (enable)
    count = count + 1;
end

medium

A. Using blocking assignment inside sequential always block

B. Missing sensitivity to reset signal

C. Using non-blocking assignment instead of blocking

D. No error, code is synthesizable

Solution

1. Step 1: Check assignment type in sequential block

   Sequential blocks triggered by clock edges should use non-blocking assignments (<=).

2. Step 2: Identify error in code

   The code uses blocking assignment (=) inside a clocked always block, which can cause incorrect synthesis.

3. Final Answer:

   Using blocking assignment inside sequential always block -> Option A

4. Quick Check:

   Sequential always blocks need non-blocking assignments [OK]

Hint: Use <= in clocked always blocks, not = [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Ignoring reset signals in counters
• Assuming blocking assignments are always okay

5. You want to design a 4-bit counter that resets asynchronously and counts up on each clock edge only when enable is high. Which of the following code snippets follows synthesis rules correctly?

hard

A. always @(posedge clk or posedge reset) begin
if (reset) count = 0;
else if (enable) count <= count + 1;
end

B. always @(posedge clk) begin
if (reset) count = 0;
else if (enable) count = count + 1;
end

C. always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

D. always @(posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

Solution

1. Step 1: Check asynchronous reset sensitivity

   Asynchronous reset requires reset in sensitivity list (posedge reset).

2. Step 2: Verify assignment types and conditions

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end uses non-blocking assignments (<=) and includes reset in sensitivity list, correctly implementing async reset and enable control.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end -> Option C

4. Quick Check:

   Async reset in sensitivity + non-blocking assignments [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Omitting reset from sensitivity list for async reset
• Mixing blocking and non-blocking assignments