Why synthesis rules matter in Verilog - Performance Analysis

Time Complexity: Why synthesis rules matter

O(n)

Understanding Time Complexity

When writing Verilog code, how synthesis rules are followed affects how hardware is built and how fast it runs.

We want to see how the number of operations grows as the design size grows, based on synthesis rules.

Scenario Under Consideration

Analyze the time complexity of the following Verilog code snippet.

module counter(input clk, input reset, output reg [7:0] count);
  always @(posedge clk or posedge reset) begin
    if (reset)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule
    

This code describes a simple 8-bit counter that increments on each clock cycle or resets to zero.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The counter increments by 1 on every clock cycle.
• How many times: This happens once per clock cycle, repeating indefinitely.

How Execution Grows With Input

Explain the growth pattern intuitively.

Input Size (n)	Approx. Operations
10 clock cycles	10 increments
100 clock cycles	100 increments
1000 clock cycles	1000 increments

Pattern observation: The number of increments grows directly with the number of clock cycles.

Final Time Complexity

Time Complexity: O(n)

This means the work done grows linearly with the number of clock cycles or input size.

Common Mistake

[X] Wrong: "The counter increments instantly for all values at once, so time does not grow with input."

[OK] Correct: Each increment happens one step at a time per clock cycle, so time grows with how many increments happen.

Interview Connect

Understanding how synthesis rules affect operation counts helps you explain hardware speed and resource use clearly in interviews.

Self-Check

"What if the counter was 16 bits instead of 8 bits? How would the time complexity change?"

Practice

1. Why is it important to follow synthesis rules when writing Verilog code?

easy

A. Because synthesis rules ensure the code can be converted into real hardware

B. Because synthesis rules make the code run faster in simulation

C. Because synthesis rules help the code look cleaner

D. Because synthesis rules allow the code to run on any software

Solution

1. Step 1: Understand synthesis purpose

   Synthesis converts Verilog code into hardware circuits.

2. Step 2: Connect rules to hardware creation

   Following synthesis rules ensures the code can be correctly transformed into hardware.

3. Final Answer:

   Because synthesis rules ensure the code can be converted into real hardware -> Option A

4. Quick Check:

   Synthesis rules = hardware conversion [OK]

Hint: Synthesis rules = code to hardware conversion [OK]

Common Mistakes:

• Confusing synthesis rules with simulation speed
• Thinking synthesis rules only affect code style
• Believing synthesis rules affect software compatibility

2. Which of the following Verilog code snippets follows synthesis rules for combinational logic?

easy

A. always @(posedge clk) begin out = in1 & in2; end

B. always @(negedge clk) begin out <= in1 | in2; end

C. initial begin out = 1'b0; end

D. always @(*) begin out = in1 & in2; end

Solution

1. Step 1: Identify combinational logic sensitivity list

   Combinational logic uses always @(*) to react to input changes.

2. Step 2: Check each option

   always @(*) begin out = in1 & in2; end uses always @(*) with blocking assignment, correct for combinational logic.

3. Final Answer:

   always @(*) begin out = in1 & in2; end -> Option D

4. Quick Check:

   Combinational logic uses always @(*) [OK]

Hint: Combinational logic uses always @(*) blocks [OK]

Common Mistakes:

• Using clock edges for combinational logic
• Using non-blocking assignments in combinational always blocks
• Using initial blocks for synthesis

3. What will be the output of this Verilog code after synthesis if clk is a clock and reset is active high?

module test(input clk, reset, input d, output reg q);
  always @(posedge clk or posedge reset) begin
    if (reset) q <= 0;
    else q <= d;
  end
endmodule

medium

A. q follows d asynchronously ignoring reset

B. q resets to 0 when reset is high, else q follows d on clock edge

C. q never resets and holds previous value

D. q resets to 1 when reset is high

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clk or reset.

2. Step 2: Understand reset behavior

   If reset is high, q is set to 0 immediately (asynchronous reset). Otherwise, q follows d on clock edge.

3. Final Answer:

   q resets to 0 when reset is high, else q follows d on clock edge -> Option B

4. Quick Check:

   Asynchronous reset sets q=0, else q=d [OK]

Hint: Check sensitivity list for async reset behavior [OK]

Common Mistakes:

• Assuming reset is synchronous
• Ignoring reset in output behavior
• Confusing reset value as 1 instead of 0

4. Identify the synthesis error in this Verilog code:

always @(posedge clk) begin
  if (enable)
    count = count + 1;
end

medium

A. Using blocking assignment inside sequential always block

B. Missing sensitivity to reset signal

C. Using non-blocking assignment instead of blocking

D. No error, code is synthesizable

Solution

1. Step 1: Check assignment type in sequential block

   Sequential blocks triggered by clock edges should use non-blocking assignments (<=).

2. Step 2: Identify error in code

   The code uses blocking assignment (=) inside a clocked always block, which can cause incorrect synthesis.

3. Final Answer:

   Using blocking assignment inside sequential always block -> Option A

4. Quick Check:

   Sequential always blocks need non-blocking assignments [OK]

Hint: Use <= in clocked always blocks, not = [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Ignoring reset signals in counters
• Assuming blocking assignments are always okay

5. You want to design a 4-bit counter that resets asynchronously and counts up on each clock edge only when enable is high. Which of the following code snippets follows synthesis rules correctly?

hard

A. always @(posedge clk or posedge reset) begin
if (reset) count = 0;
else if (enable) count <= count + 1;
end

B. always @(posedge clk) begin
if (reset) count = 0;
else if (enable) count = count + 1;
end

C. always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

D. always @(posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
end

Solution

1. Step 1: Check asynchronous reset sensitivity

   Asynchronous reset requires reset in sensitivity list (posedge reset).

2. Step 2: Verify assignment types and conditions

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end uses non-blocking assignments (<=) and includes reset in sensitivity list, correctly implementing async reset and enable control.

3. Final Answer:

   always @(posedge clk or posedge reset) begin if (reset) count <= 0; else if (enable) count <= count + 1; end -> Option C

4. Quick Check:

   Async reset in sensitivity + non-blocking assignments [OK]

Hint: Async reset needs posedge reset in sensitivity list [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Omitting reset from sensitivity list for async reset
• Mixing blocking and non-blocking assignments