Why hierarchy is essential for large designs in Verilog - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a module named 'adder'.

Verilog

module [1] (input a, input b, output sum);

Drag options to blanks, or click blank then click option'

Aadder

Bsum

Cinput

Doutput

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'input' or 'output' as module name.

Forgetting to name the module.

The module name must be 'adder' to define the adder block.

2fill in blank

medium

Complete the code to instantiate the 'adder' module inside 'top_module'.

Verilog

adder [1] (.a(a), .b(b), .sum(sum));

Drag options to blanks, or click blank then click option'

Atop

Bu_adder

Cinst_adder

Dadder_inst

Attempts:

3 left

💡 Hint

Common Mistakes

Using the module name as instance name.

Using invalid names with spaces.

The instance name 'u_adder' is a common convention for module instances.

3fill in blank

hard

Fix the error in the module declaration by completing the blank.

Verilog

module top_module([1] a, input b, output sum);

Drag options to blanks, or click blank then click option'

Aoutput

Bendmodule

Cwire

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Writing 'output' first.

Forgetting to declare ports.

The port list must start with the keyword 'input' before the signals.

4fill in blank

hard

Fill both blanks to complete the hierarchical instantiation and connection.

Verilog

module top_module(input a, input b, output sum);
  wire [1];
  adder [2] (.a(a), .b(b), .sum([1]));
  assign sum = [1];
endmodule

Drag options to blanks, or click blank then click option'

Asum_wire

Bu_adder

Cadder_inst

Dtemp

Attempts:

3 left

💡 Hint

Common Mistakes

Using the same name for wire and instance.

Not declaring the wire.

The wire 'sum_wire' connects the adder output, and 'u_adder' is the instance name.

5fill in blank

hard

Fill all three blanks to create a hierarchical design with two adders connected.

Verilog

module top_module(input a, input b, input c, output sum);
  wire [1], [2];
  adder [3] (.a(a), .b(b), .sum([1]));
  adder u_adder2 (.a([1]), .b(c), .sum([2]));
  assign sum = [2];
endmodule

Drag options to blanks, or click blank then click option'

Asum1

Bsum2

Cu_adder1

Du_adder3

Attempts:

3 left

💡 Hint

Common Mistakes

Using the same wire name twice.

Using wrong instance names.

'sum1' and 'sum2' are wires connecting the two adders, and 'u_adder1' is the first adder instance.

Practice

1. Why is hierarchy important in large Verilog designs?

easy

A. It allows using only one module for everything.

B. It makes the code run faster automatically.

C. It breaks the design into smaller, manageable modules.

D. It removes the need for testbenches.

Solution

1. Step 1: Understand the role of hierarchy

   Hierarchy divides a large design into smaller modules, making it easier to manage.

2. Step 2: Compare options

   Only breaking into smaller modules helps organize and debug large designs effectively.

3. Final Answer:

   It breaks the design into smaller, manageable modules. -> Option C

4. Quick Check:

   Hierarchy = Smaller modules [OK]

Hint: Think: big design = many small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up code automatically
• Believing hierarchy removes need for testbenches
• Thinking one module can handle everything

2. Which of the following is the correct way to instantiate a module named alu inside another module in Verilog?

easy

A. call alu();

B. module alu();

C. inst alu();

D. alu u1();

Solution

1. Step 1: Recall module instantiation syntax

   In Verilog, to use a module inside another, write: module_name instance_name();

2. Step 2: Check options

   Only alu u1(); matches this syntax: alu u1();

3. Final Answer:

   alu u1(); -> Option D

4. Quick Check:

   Module instantiation = module_name instance_name() [OK]

Hint: Use: moduleName instanceName(); [OK]

Common Mistakes:

• Writing 'module' keyword to instantiate
• Using 'inst' or 'call' which are invalid
• Omitting instance name

3. Given the following Verilog code, what will be the output of the top module's out signal?

module adder(input a, input b, output sum);
  assign sum = a + b;
endmodule

module top(input x, input y, output z);
  wire temp;
  adder add1(.a(x), .b(y), .sum(temp));
  assign z = temp;
endmodule

medium

A. z will be the AND of x and y

B. z will be the sum of x and y

C. z will always be 0

D. Syntax error due to missing semicolon

Solution

1. Step 1: Understand module connections

   The top module instantiates adder, connecting inputs x,y to a,b and output temp to sum.

2. Step 2: Trace signal assignment

   Adder sums a and b, so temp = x + y, then z = temp, so z = x + y.

3. Final Answer:

   z will be the sum of x and y -> Option B

4. Quick Check:

   Output z = x + y [OK]

Hint: Follow signal flow through modules [OK]

Common Mistakes:

• Confusing sum with AND operation
• Assuming output is always zero
• Thinking code has syntax errors

4. Identify the error in this Verilog code snippet that tries to instantiate a module cpu inside system:

module cpu(input clk, output reg done);
  always @(posedge clk) done <= 1'b1;
endmodule

module system(input clk, output done);
  cpu cpu_inst(clk);
endmodule

medium

A. Incorrect port connection syntax in cpu instantiation

B. Missing semicolon after module declaration

C. Output port 'done' should be declared as reg in system

D. Always block missing sensitivity list

Solution

1. Step 1: Recall module instantiation syntax

   Correct syntax is <module_name> <instance_name>(<connections for all ports in order>);

2. Step 2: Analyze the instantiation

   cpu has two ports (input clk, output done), but cpu cpu_inst(clk); provides only one connection, causing port mismatch and incorrect port connection syntax.

3. Final Answer:

   Incorrect port connection syntax in cpu instantiation -> Option A

4. Quick Check:

   Port arguments != port declarations [OK]

Hint: Check module instantiation parentheses and port connections [OK]

Common Mistakes:

• Confusing reg declaration in top module
• Omitting port connections in instantiation
• Misunderstanding sensitivity list in always block

5. You have a large Verilog design with multiple modules: cpu, memory, and io. To improve readability and reuse, which hierarchical approach is best?

hard

A. Create a top module that instantiates cpu, memory, and io modules separately.

B. Combine all code into one big module to avoid confusion.

C. Write separate modules but never instantiate them; use only one module.

D. Use only behavioral code without modules for flexibility.

Solution

1. Step 1: Understand hierarchy benefits

   Separating design into modules and instantiating them in a top module improves organization and reuse.

2. Step 2: Evaluate options

   Creating a top module that instantiates cpu, memory, and io modules separately is best practice for large designs.

3. Final Answer:

   Create a top module that instantiates cpu, memory, and io modules separately. -> Option A

4. Quick Check:

   Top module with submodules = Create a top module that instantiates cpu, memory, and io modules separately. [OK]

Hint: Use a top module to organize submodules [OK]

Common Mistakes:

• Putting all code in one module
• Not instantiating modules at all
• Avoiding modules for behavioral code only