Why hierarchy is essential for large designs in Verilog - Challenge Your Understanding

Challenge - 5 Problems

🧠 Conceptual

intermediate

Why use hierarchy in large Verilog designs?

In large Verilog designs, why is hierarchy important?

A It removes the need for testbenches in simulation.

B It helps organize the design into smaller, manageable modules.

C It makes the design run faster on hardware automatically.

D It allows the design to use fewer logic gates.

💡 Hint

Think about how breaking a big task into smaller parts helps you understand it better.

Hierarchy breaks a large design into smaller modules, making it easier to develop, debug, and maintain.

❓ Predict Output

intermediate

Output of hierarchical module instantiation

What is the output of the following Verilog code when top module is simulated?

Verilog

module adder(input wire a, input wire b, output wire sum);
  assign sum = a ^ b;
endmodule

module top;
  reg x = 1'b1;
  reg y = 1'b0;
  wire s;
  adder u1(.a(x), .b(y), .sum(s));
  initial begin
    #1 $display("Sum = %b", s);
  end
endmodule

A Sum = 1

B Sum = 0

C Sum = x

D Simulation error

💡 Hint

Recall that XOR of 1 and 0 is 1.

The adder module outputs the XOR of inputs a and b. Since a=1 and b=0, sum=1.

🔧 Debug

advanced

Identify the hierarchy-related error

What error will occur when compiling this Verilog code?

Verilog

module child(input wire a, output wire b);
  assign b = ~a;
endmodule

module parent;
  wire w;
  child u1(.a(x), .b(w));
endmodule

A Error: Module 'child' not found

B Error: Output 'b' cannot be wire

C No error, code compiles successfully

D Error: Undeclared variable 'x' in parent module

💡 Hint

Check if all signals used in module instantiations are declared.

The parent module instantiates child with input 'x' which is not declared anywhere, causing a compilation error.

📝 Syntax

advanced

Correct hierarchical instantiation syntax

Which option shows the correct way to instantiate a module foo with ports in and out inside another module?

A foo instance1(in, out);

B foo instance1(in => in, out => out);

C foo instance1(.in(in), .out(out));

D foo instance1(in: in, out: out);

💡 Hint

Remember Verilog uses dot and parentheses for named port connections.

Option C uses correct named port mapping syntax: dot followed by port name and parentheses with signal.

🚀 Application

expert

Calculate number of modules in hierarchical design

A top-level module instantiates 3 submodules. Each submodule instantiates 2 sub-submodules. How many total modules are instantiated in the design?

A 9

B 12

C 3

D 6

💡 Hint

3 submodules + 3*2 sub-submodules = 9.

The top-level instantiates 3 submodules, and each of those instantiates 2 sub-submodules, for a total of 3 + 6 = 9 instantiated modules. The top-level itself is not instantiated by any other module.

Practice

1. Why is hierarchy important in large Verilog designs?

easy

A. It allows using only one module for everything.

B. It makes the code run faster automatically.

C. It breaks the design into smaller, manageable modules.

D. It removes the need for testbenches.

Solution

1. Step 1: Understand the role of hierarchy

   Hierarchy divides a large design into smaller modules, making it easier to manage.

2. Step 2: Compare options

   Only breaking into smaller modules helps organize and debug large designs effectively.

3. Final Answer:

   It breaks the design into smaller, manageable modules. -> Option C

4. Quick Check:

   Hierarchy = Smaller modules [OK]

Hint: Think: big design = many small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up code automatically
• Believing hierarchy removes need for testbenches
• Thinking one module can handle everything

2. Which of the following is the correct way to instantiate a module named alu inside another module in Verilog?

easy

A. call alu();

B. module alu();

C. inst alu();

D. alu u1();

Solution

1. Step 1: Recall module instantiation syntax

   In Verilog, to use a module inside another, write: module_name instance_name();

2. Step 2: Check options

   Only alu u1(); matches this syntax: alu u1();

3. Final Answer:

   alu u1(); -> Option D

4. Quick Check:

   Module instantiation = module_name instance_name() [OK]

Hint: Use: moduleName instanceName(); [OK]

Common Mistakes:

• Writing 'module' keyword to instantiate
• Using 'inst' or 'call' which are invalid
• Omitting instance name

3. Given the following Verilog code, what will be the output of the top module's out signal?

module adder(input a, input b, output sum);
  assign sum = a + b;
endmodule

module top(input x, input y, output z);
  wire temp;
  adder add1(.a(x), .b(y), .sum(temp));
  assign z = temp;
endmodule

medium

A. z will be the AND of x and y

B. z will be the sum of x and y

C. z will always be 0

D. Syntax error due to missing semicolon

Solution

1. Step 1: Understand module connections

   The top module instantiates adder, connecting inputs x,y to a,b and output temp to sum.

2. Step 2: Trace signal assignment

   Adder sums a and b, so temp = x + y, then z = temp, so z = x + y.

3. Final Answer:

   z will be the sum of x and y -> Option B

4. Quick Check:

   Output z = x + y [OK]

Hint: Follow signal flow through modules [OK]

Common Mistakes:

• Confusing sum with AND operation
• Assuming output is always zero
• Thinking code has syntax errors

4. Identify the error in this Verilog code snippet that tries to instantiate a module cpu inside system:

module cpu(input clk, output reg done);
  always @(posedge clk) done <= 1'b1;
endmodule

module system(input clk, output done);
  cpu cpu_inst(clk);
endmodule

medium

A. Incorrect port connection syntax in cpu instantiation

B. Missing semicolon after module declaration

C. Output port 'done' should be declared as reg in system

D. Always block missing sensitivity list

Solution

1. Step 1: Recall module instantiation syntax

   Correct syntax is <module_name> <instance_name>(<connections for all ports in order>);

2. Step 2: Analyze the instantiation

   cpu has two ports (input clk, output done), but cpu cpu_inst(clk); provides only one connection, causing port mismatch and incorrect port connection syntax.

3. Final Answer:

   Incorrect port connection syntax in cpu instantiation -> Option A

4. Quick Check:

   Port arguments != port declarations [OK]

Hint: Check module instantiation parentheses and port connections [OK]

Common Mistakes:

• Confusing reg declaration in top module
• Omitting port connections in instantiation
• Misunderstanding sensitivity list in always block

5. You have a large Verilog design with multiple modules: cpu, memory, and io. To improve readability and reuse, which hierarchical approach is best?

hard

A. Create a top module that instantiates cpu, memory, and io modules separately.

B. Combine all code into one big module to avoid confusion.

C. Write separate modules but never instantiate them; use only one module.

D. Use only behavioral code without modules for flexibility.

Solution

1. Step 1: Understand hierarchy benefits

   Separating design into modules and instantiating them in a top module improves organization and reuse.

2. Step 2: Evaluate options

   Creating a top module that instantiates cpu, memory, and io modules separately is best practice for large designs.

3. Final Answer:

   Create a top module that instantiates cpu, memory, and io modules separately. -> Option A

4. Quick Check:

   Top module with submodules = Create a top module that instantiates cpu, memory, and io modules separately. [OK]

Hint: Use a top module to organize submodules [OK]

Common Mistakes:

• Putting all code in one module
• Not instantiating modules at all
• Avoiding modules for behavioral code only