Why hierarchy is essential for large designs in Verilog - See It in Action

Why hierarchy is essential for large designs

📖 Scenario: Imagine you are designing a big digital system like a simple calculator. Instead of writing all the logic in one place, you break it into smaller parts like adders, subtractors, and controllers. This way, your design is easier to understand and manage.

🎯 Goal: You will create a small Verilog project that shows how hierarchy helps organize a large design by building a simple calculator using smaller modules.

📋 What You'll Learn

Create a top module called calculator

Create smaller modules called adder and subtractor

Use hierarchy by instantiating adder and subtractor inside calculator

Show how inputs flow through the hierarchy and produce outputs

💡 Why This Matters

🌍 Real World

Large digital systems like CPUs, GPUs, and communication devices use hierarchy to organize millions of components efficiently.

💼 Career

Understanding hierarchy is essential for hardware engineers to design, test, and maintain complex digital circuits professionally.

1

Create the adder module

Write a Verilog module called adder that has two 4-bit inputs called a and b, and one 4-bit output called sum. The module should add a and b and assign the result to sum.

Verilog

// Your code here
// Create module adder with inputs a, b and output sum

Hint

Use module keyword to define the adder. Use assign to add inputs.

2

Create the subtractor module

Write a Verilog module called subtractor that has two 4-bit inputs called a and b, and one 4-bit output called diff. The module should subtract b from a and assign the result to diff.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

// Your code here
// Create module subtractor with inputs a, b and output diff

Hint

Similar to adder, but use subtraction.

3

Create the top-level calculator module with hierarchy

Write a Verilog module called calculator that has two 4-bit inputs called in1 and in2, and two 4-bit outputs called sum_out and diff_out. Inside this module, instantiate the adder and subtractor modules. Connect in1 and in2 to both modules and connect their outputs to sum_out and diff_out respectively.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

module subtractor(input [3:0] a, input [3:0] b, output [3:0] diff);
    assign diff = a - b;
endmodule

// Your code here
// Create module calculator with inputs in1, in2 and outputs sum_out, diff_out
// Instantiate adder and subtractor inside calculator

Hint

Use module instantiation syntax with dot connections to connect signals.

4

Test the calculator module output

Write a testbench module called testbench that declares two 4-bit registers a and b, and two 4-bit wires sum and diff. Instantiate the calculator module connecting a, b, sum, and diff. Assign a = 4 and b = 3. Use $display to print the values of a, b, sum, and diff. Run the simulation for one time unit.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

module subtractor(input [3:0] a, input [3:0] b, output [3:0] diff);
    assign diff = a - b;
endmodule

module calculator(input [3:0] in1, input [3:0] in2, output [3:0] sum_out, output [3:0] diff_out);
    adder add_inst(.a(in1), .b(in2), .sum(sum_out));
    subtractor sub_inst(.a(in1), .b(in2), .diff(diff_out));
endmodule

// Your code here
// Create testbench module
// Declare registers a, b and wires sum, diff
// Instantiate calculator
// Assign a=4, b=3
// Display a, b, sum, diff
// Run simulation for 1 time unit

Hint

Use reg for inputs and wire for outputs. Use $display to print values.

Practice

1. Why is hierarchy important in large Verilog designs?

easy

A. It allows using only one module for everything.

B. It makes the code run faster automatically.

C. It breaks the design into smaller, manageable modules.

D. It removes the need for testbenches.

Solution

1. Step 1: Understand the role of hierarchy

   Hierarchy divides a large design into smaller modules, making it easier to manage.

2. Step 2: Compare options

   Only breaking into smaller modules helps organize and debug large designs effectively.

3. Final Answer:

   It breaks the design into smaller, manageable modules. -> Option C

4. Quick Check:

   Hierarchy = Smaller modules [OK]

Hint: Think: big design = many small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up code automatically
• Believing hierarchy removes need for testbenches
• Thinking one module can handle everything

2. Which of the following is the correct way to instantiate a module named alu inside another module in Verilog?

easy

A. call alu();

B. module alu();

C. inst alu();

D. alu u1();

Solution

1. Step 1: Recall module instantiation syntax

   In Verilog, to use a module inside another, write: module_name instance_name();

2. Step 2: Check options

   Only alu u1(); matches this syntax: alu u1();

3. Final Answer:

   alu u1(); -> Option D

4. Quick Check:

   Module instantiation = module_name instance_name() [OK]

Hint: Use: moduleName instanceName(); [OK]

Common Mistakes:

• Writing 'module' keyword to instantiate
• Using 'inst' or 'call' which are invalid
• Omitting instance name

3. Given the following Verilog code, what will be the output of the top module's out signal?

module adder(input a, input b, output sum);
  assign sum = a + b;
endmodule

module top(input x, input y, output z);
  wire temp;
  adder add1(.a(x), .b(y), .sum(temp));
  assign z = temp;
endmodule

medium

A. z will be the AND of x and y

B. z will be the sum of x and y

C. z will always be 0

D. Syntax error due to missing semicolon

Solution

1. Step 1: Understand module connections

   The top module instantiates adder, connecting inputs x,y to a,b and output temp to sum.

2. Step 2: Trace signal assignment

   Adder sums a and b, so temp = x + y, then z = temp, so z = x + y.

3. Final Answer:

   z will be the sum of x and y -> Option B

4. Quick Check:

   Output z = x + y [OK]

Hint: Follow signal flow through modules [OK]

Common Mistakes:

• Confusing sum with AND operation
• Assuming output is always zero
• Thinking code has syntax errors

4. Identify the error in this Verilog code snippet that tries to instantiate a module cpu inside system:

module cpu(input clk, output reg done);
  always @(posedge clk) done <= 1'b1;
endmodule

module system(input clk, output done);
  cpu cpu_inst(clk);
endmodule

medium

A. Incorrect port connection syntax in cpu instantiation

B. Missing semicolon after module declaration

C. Output port 'done' should be declared as reg in system

D. Always block missing sensitivity list

Solution

1. Step 1: Recall module instantiation syntax

   Correct syntax is <module_name> <instance_name>(<connections for all ports in order>);

2. Step 2: Analyze the instantiation

   cpu has two ports (input clk, output done), but cpu cpu_inst(clk); provides only one connection, causing port mismatch and incorrect port connection syntax.

3. Final Answer:

   Incorrect port connection syntax in cpu instantiation -> Option A

4. Quick Check:

   Port arguments != port declarations [OK]

Hint: Check module instantiation parentheses and port connections [OK]

Common Mistakes:

• Confusing reg declaration in top module
• Omitting port connections in instantiation
• Misunderstanding sensitivity list in always block

5. You have a large Verilog design with multiple modules: cpu, memory, and io. To improve readability and reuse, which hierarchical approach is best?

hard

A. Create a top module that instantiates cpu, memory, and io modules separately.

B. Combine all code into one big module to avoid confusion.

C. Write separate modules but never instantiate them; use only one module.

D. Use only behavioral code without modules for flexibility.

Solution

1. Step 1: Understand hierarchy benefits

   Separating design into modules and instantiating them in a top module improves organization and reuse.

2. Step 2: Evaluate options

   Creating a top module that instantiates cpu, memory, and io modules separately is best practice for large designs.

3. Final Answer:

   Create a top module that instantiates cpu, memory, and io modules separately. -> Option A

4. Quick Check:

   Top module with submodules = Create a top module that instantiates cpu, memory, and io modules separately. [OK]

Hint: Use a top module to organize submodules [OK]

Common Mistakes:

• Putting all code in one module
• Not instantiating modules at all
• Avoiding modules for behavioral code only