Task and function in testbenches in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to define a simple task that prints a message.

Verilog

task display_message();
  begin
    $display([1]);
  end
endtask

Drag options to blanks, or click blank then click option'

A"Hello, Testbench!"

BHello, Testbench!

C'Hello, Testbench!'

DHello Testbench

Attempts:

3 left

💡 Hint

Common Mistakes

Forgetting the double quotes around the string.

Using single quotes instead of double quotes.

The $display statement requires a string literal enclosed in double quotes.

2fill in blank

medium

Complete the code to call the task 'display_message' inside an initial block.

Verilog

initial begin
  [1];
end

Drag options to blanks, or click blank then click option'

Acall display_message

Bdisplay_message()

Ccall display_message()

Ddisplay_message

Attempts:

3 left

💡 Hint

Common Mistakes

Calling the task without parentheses.

Using 'call' keyword which is not used in Verilog.

Tasks are called with parentheses even if they have no arguments.

3fill in blank

hard

Fix the error in the function definition that returns the sum of two inputs.

Verilog

function integer add_two;
  input integer a, b;
  begin
    add_two = a [1] b;
  end
endfunction

Drag options to blanks, or click blank then click option'

A*

B-

C+

D/

Attempts:

3 left

💡 Hint

Common Mistakes

Using subtraction or multiplication instead of addition.

Forgetting to assign the function name the result.

The function should add the two inputs using the '+' operator.

4fill in blank

hard

Fill both blanks to complete the task that waits for a signal to be high and then displays a message.

Verilog

task wait_and_display(input signal);
  begin
    wait (signal [1] 1);
    $display([2]);
  end
endtask

Drag options to blanks, or click blank then click option'

A==

B!=

C"Signal is high!"

D"Signal is low!"

Attempts:

3 left

💡 Hint

Common Mistakes

Using '!=' instead of '==' in the wait condition.

Displaying the wrong message.

The task waits until the signal equals 1, then displays the message that the signal is high.

5fill in blank

hard

Fill all three blanks to complete the function that returns the maximum of two inputs.

Verilog

function integer max_val;
  input integer a, b;
  begin
    if (a [1] b) begin
      max_val = [2];
    end else begin
      max_val = [3];
    end
  end
endfunction

Drag options to blanks, or click blank then click option'

A>

Ba

Cb

D<

Attempts:

3 left

💡 Hint

Common Mistakes

Using '<' instead of '>' in the condition.

Swapping the return values for true and false cases.

The function compares a and b using '>', returns a if true, else returns b.

Practice

1. Which of the following is true about tasks in Verilog testbenches?

easy

A. Tasks cannot have input or output arguments.

B. Tasks can include timing controls like delays.

C. Tasks must always return a value.

D. Tasks are used only for synthesizable code.

Solution

1. Step 1: Understand the role of tasks

   Tasks in Verilog testbenches are used to group statements and can include timing controls such as delays.

2. Step 2: Compare tasks and functions

   Unlike functions, tasks do not return values but can have timing controls and input/output arguments.

3. Final Answer:

   Tasks can include timing controls like delays. -> Option B

4. Quick Check:

   Tasks allow delays = C [OK]

Hint: Remember: tasks can have delays; functions cannot. [OK]

Common Mistakes:

• Thinking tasks must return a value
• Assuming tasks cannot have arguments
• Confusing tasks with synthesizable modules

2. Which of the following is the correct syntax to define a function in Verilog testbench?

easy

A. function void my_func(); begin ... end endfunction

B. task integer my_func(); begin ... end endtask

C. function integer my_func(); begin ... return 1; end endfunction

D. function my_func(); begin ... end

Solution

1. Step 1: Identify function syntax

   Functions must specify a return type and use 'function' and 'endfunction' keywords.

2. Step 2: Check return statement and type

   function integer my_func(); begin ... return 1; end endfunction correctly defines a function returning integer and includes a return statement.

3. Final Answer:

   function integer my_func(); begin ... return 1; end endfunction -> Option C

4. Quick Check:

   Function syntax with return type and return statement = B [OK]

Hint: Functions need return type and return statement. [OK]

Common Mistakes:

• Using 'void' as function return type
• Defining functions with 'task' keyword
• Omitting 'endfunction' keyword

3. What is the output of this Verilog testbench code snippet?

module tb;
  integer result;
  initial begin
    result = add_two(5);
    $display("Result = %0d", result);
  end
  function integer add_two(input integer x);
    add_two = x + 2;
  endfunction
endmodule

medium

A. Result = 7

B. Result = 5

C. Result = 2

D. Syntax error

Solution

1. Step 1: Understand function call and return

   The function 'add_two' takes input 5 and returns 5 + 2 = 7.

2. Step 2: Check display output

   The $display prints the returned value stored in 'result', which is 7.

3. Final Answer:

   Result = 7 -> Option A

4. Quick Check:

   Function returns 5+2=7 = A [OK]

Hint: Functions return values; check the return expression. [OK]

Common Mistakes:

• Confusing function return with task behavior
• Ignoring the return value assignment
• Assuming syntax error due to missing semicolons

4. Identify the error in this Verilog task definition:

task display_msg;
  input string msg;
  begin
    #5 $display(msg);
  end
endtask

medium

A. Missing semicolon after task name.

B. Delay (#5) is not allowed inside tasks.

C. Tasks cannot have input arguments.

D. The input argument type 'string' is not supported in Verilog tasks.

Solution

1. Step 1: Check argument types in tasks

   Verilog does not support 'string' type as input argument in tasks; it uses reg or wire types.

2. Step 2: Verify delay usage and syntax

   Delay (#5) is allowed in tasks, and semicolon after task name is not required.

3. Final Answer:

   The input argument type 'string' is not supported in Verilog tasks. -> Option D

4. Quick Check:

   Verilog tasks don't support 'string' type = A [OK]

Hint: Use reg or wire, not string, for task inputs. [OK]

Common Mistakes:

• Thinking delays are disallowed in tasks
• Assuming tasks cannot have inputs
• Adding unnecessary semicolons after task name

5. You want to create a testbench helper that calculates the average of three integers and waits 10 time units before returning the result. Which is the best way to implement this in Verilog?

hard

A. Use a task that calculates average, includes a #10 delay, and returns the value via output argument.

B. Use a task that calculates average and returns the value using a return statement.

C. Use a function that calculates average and returns immediately without delay.

D. Use a function that calculates average and includes a #10 delay before returning.

Solution

1. Step 1: Understand timing control in tasks and functions

   Functions cannot have delays (#10), but tasks can include delays.

2. Step 2: Return value from task

   Tasks do not return values directly but can output results via output arguments.

3. Step 3: Choose correct implementation

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument, matching requirements.

4. Final Answer:

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument. -> Option A

5. Quick Check:

   Delay needs task + output arg = D [OK]

Hint: Use tasks for delays; functions can't delay. Return via output args. [OK]

Common Mistakes:

• Trying to put delay inside a function
• Expecting tasks to return values directly
• Ignoring output arguments for tasks