Task and function in testbenches in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a Verilog task call in a testbench

What is the output of this Verilog testbench code when run?

Verilog

module test;
  reg [3:0] a, b;
  initial begin
    a = 4'd5;
    b = 4'd3;
    add_and_display(a, b);
  end

  task add_and_display(input [3:0] x, input [3:0] y);
    reg [4:0] sum;
    begin
      sum = x + y;
      $display("Sum is: %d", sum);
    end
  endtask
endmodule

A No output, syntax error

B Sum is: 53

C Sum is: 2

D Sum is: 8

💡 Hint

Remember that the task adds two 4-bit numbers and displays the result as a decimal.

The task adds the two inputs 5 and 3, resulting in 8, and displays it.

❓ Predict Output

intermediate

Function return value in a Verilog testbench

What value does the function multiply_by_two return in this testbench?

Verilog

module test;
  reg [3:0] val;
  reg [4:0] result;
  initial begin
    val = 4'd7;
    result = multiply_by_two(val);
    $display("Result: %d", result);
  end

  function [4:0] multiply_by_two(input [3:0] x);
    begin
      multiply_by_two = x << 1;
    end
  endfunction
endmodule

A Result: 28

B Result: 7

C Result: 14

D Syntax error, function missing return

💡 Hint

Left shift by 1 is the same as multiplying by 2.

The function shifts 7 left by 1 bit, which equals 14.

❓ Predict Output

advanced

Task with delay and output timing in Verilog testbench

What will be the order and timing of the outputs when this testbench runs?

Verilog

module test;
  initial begin
    $timeformat(-9, 1, " ns", 6);
    display_message();
  end

  task display_message;
    begin
      $display("Start time: %t", $time);
      #5;
      $display("After 5 time units: %t", $time);
      #10;
      $display("After 15 time units: %t", $time);
    end
  endtask
endmodule

A

Start time: 0 ns
After 5 time units: 10 ns
After 15 time units: 20 ns

B

Start time: 0 ns
After 5 time units: 5 ns
After 15 time units: 15 ns

C

Start time: 5 ns
After 5 time units: 10 ns
After 15 time units: 15 ns

D No output, task not called

💡 Hint

Delays inside a task add to the simulation time sequentially.

The task prints at time 0, then waits 5 units, prints, waits 10 more units, then prints again.

❓ Predict Output

advanced

Function with conditional logic in Verilog testbench

What is the output of this testbench code?

Verilog

module test;
  reg [3:0] val;
  reg [3:0] res;
  initial begin
    val = 4'd9;
    res = check_and_double(val);
    $display("Result: %d", res);
  end

  function [3:0] check_and_double(input [3:0] x);
    begin
      if (x > 8)
        check_and_double = x * 2;
      else
        check_and_double = x;
    end
  endfunction
endmodule

A Result: 2

B Result: 18

C Result: 9

D Result: 0

💡 Hint

Remember the function returns a 4-bit value, so multiplication may overflow.

9 * 2 = 18 decimal, which is 10010 binary. Only 4 bits are stored, so lower 4 bits are 0010 (2 decimal).

❓ Predict Output

expert

Task modifying variables by reference in Verilog testbench

What is the value of out_val after this testbench runs?

Verilog

module test;
  reg [3:0] in_val, out_val;
  initial begin
    in_val = 4'd7;
    out_val = 4'd0;
    modify_values(in_val, out_val);
    $display("out_val: %d", out_val);
  end

  task modify_values(input [3:0] in_val, output [3:0] out_val);
    begin
      out_val = in_val + 3;
    end
  endtask
endmodule

A out_val: 10

B out_val: 0

C out_val: 7

D Syntax error: output reg not allowed in task port

💡 Hint

Output ports in tasks can modify variables passed by reference.

The task adds 3 to in_val (7), so out_val becomes 10.

Practice

1. Which of the following is true about tasks in Verilog testbenches?

easy

A. Tasks cannot have input or output arguments.

B. Tasks can include timing controls like delays.

C. Tasks must always return a value.

D. Tasks are used only for synthesizable code.

Solution

1. Step 1: Understand the role of tasks

   Tasks in Verilog testbenches are used to group statements and can include timing controls such as delays.

2. Step 2: Compare tasks and functions

   Unlike functions, tasks do not return values but can have timing controls and input/output arguments.

3. Final Answer:

   Tasks can include timing controls like delays. -> Option B

4. Quick Check:

   Tasks allow delays = C [OK]

Hint: Remember: tasks can have delays; functions cannot. [OK]

Common Mistakes:

• Thinking tasks must return a value
• Assuming tasks cannot have arguments
• Confusing tasks with synthesizable modules

2. Which of the following is the correct syntax to define a function in Verilog testbench?

easy

A. function void my_func(); begin ... end endfunction

B. task integer my_func(); begin ... end endtask

C. function integer my_func(); begin ... return 1; end endfunction

D. function my_func(); begin ... end

Solution

1. Step 1: Identify function syntax

   Functions must specify a return type and use 'function' and 'endfunction' keywords.

2. Step 2: Check return statement and type

   function integer my_func(); begin ... return 1; end endfunction correctly defines a function returning integer and includes a return statement.

3. Final Answer:

   function integer my_func(); begin ... return 1; end endfunction -> Option C

4. Quick Check:

   Function syntax with return type and return statement = B [OK]

Hint: Functions need return type and return statement. [OK]

Common Mistakes:

• Using 'void' as function return type
• Defining functions with 'task' keyword
• Omitting 'endfunction' keyword

3. What is the output of this Verilog testbench code snippet?

module tb;
  integer result;
  initial begin
    result = add_two(5);
    $display("Result = %0d", result);
  end
  function integer add_two(input integer x);
    add_two = x + 2;
  endfunction
endmodule

medium

A. Result = 7

B. Result = 5

C. Result = 2

D. Syntax error

Solution

1. Step 1: Understand function call and return

   The function 'add_two' takes input 5 and returns 5 + 2 = 7.

2. Step 2: Check display output

   The $display prints the returned value stored in 'result', which is 7.

3. Final Answer:

   Result = 7 -> Option A

4. Quick Check:

   Function returns 5+2=7 = A [OK]

Hint: Functions return values; check the return expression. [OK]

Common Mistakes:

• Confusing function return with task behavior
• Ignoring the return value assignment
• Assuming syntax error due to missing semicolons

4. Identify the error in this Verilog task definition:

task display_msg;
  input string msg;
  begin
    #5 $display(msg);
  end
endtask

medium

A. Missing semicolon after task name.

B. Delay (#5) is not allowed inside tasks.

C. Tasks cannot have input arguments.

D. The input argument type 'string' is not supported in Verilog tasks.

Solution

1. Step 1: Check argument types in tasks

   Verilog does not support 'string' type as input argument in tasks; it uses reg or wire types.

2. Step 2: Verify delay usage and syntax

   Delay (#5) is allowed in tasks, and semicolon after task name is not required.

3. Final Answer:

   The input argument type 'string' is not supported in Verilog tasks. -> Option D

4. Quick Check:

   Verilog tasks don't support 'string' type = A [OK]

Hint: Use reg or wire, not string, for task inputs. [OK]

Common Mistakes:

• Thinking delays are disallowed in tasks
• Assuming tasks cannot have inputs
• Adding unnecessary semicolons after task name

5. You want to create a testbench helper that calculates the average of three integers and waits 10 time units before returning the result. Which is the best way to implement this in Verilog?

hard

A. Use a task that calculates average, includes a #10 delay, and returns the value via output argument.

B. Use a task that calculates average and returns the value using a return statement.

C. Use a function that calculates average and returns immediately without delay.

D. Use a function that calculates average and includes a #10 delay before returning.

Solution

1. Step 1: Understand timing control in tasks and functions

   Functions cannot have delays (#10), but tasks can include delays.

2. Step 2: Return value from task

   Tasks do not return values directly but can output results via output arguments.

3. Step 3: Choose correct implementation

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument, matching requirements.

4. Final Answer:

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument. -> Option A

5. Quick Check:

   Delay needs task + output arg = D [OK]

Hint: Use tasks for delays; functions can't delay. Return via output args. [OK]

Common Mistakes:

• Trying to put delay inside a function
• Expecting tasks to return values directly
• Ignoring output arguments for tasks